201934744

201934744's Stars

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.4k1381.7k871

• verilog-to-routing/vtr-verilog-to-routing

  Verilog to Routing -- Open Source CAD Flow for FPGA Research

  Language:C++1k681k387

• lnis-uofu/OpenFPGA

  An Open-source FPGA IP Generator

  Language:Verilog81943442160

• f4pga/prjxray

  Documenting the Xilinx 7-series bit-stream format.

  Language:Python75760478148

• emsec/hal

  HAL – The Hardware Analyzer

  Language:C++6232613976

• YosysHQ/arachne-pnr

  Place and route tool for FPGAs

  Language:C++413637172

• chipsalliance/f4pga

  FOSS Flow For FPGA

  Language:Python352174448

• chipsalliance/f4pga-examples

  Example designs showing different ways to use F4PGA toolchains.

  Language:Verilog2632416677

• chipsalliance/yosys-f4pga-plugins

  Plugins for Yosys developed as part of the F4PGA project.

  Language:Verilog821812146

• djn3m0/debit

  Reverse-engineering tools for FPGA bitstreams, Altera and Xilinx

  Language:C775034

• f4pga/prjuray

  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

  Language:SystemVerilog70192113

• FPGA-Research-Manchester/fos

  FOS - FPGA Operating System

  Language:VHDL6211410

• f4pga/prjtrellis

  Documenting the Lattice ECP5 bit-stream format.

  Language:Python49403

• byuccl/RapidSmith2

  RapidSmith2 - the Vivado successor to RapidSmith. Released Jan 4, 2017.

  Language:Java411118313

• byuccl/tincr

  A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite

  Language:Tcl39113219

• SymbiFlow/vtr-verilog-to-routing

  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research

  Language:C++37168112

• SymbiFlow/yosys

  SymbiFlow WIP changes for Yosys Open SYnthesis Suite

  Language:C++3710299

• f4pga/icestorm

  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)

  Language:Python32506

• khoapham/bitman

  Language:C217212

• SymbiFlow/nextpnr

  nextpnr portable FPGA place and route tool

  Language:C++209132

• khoapham/efcad

  Language:Tcl14511

• FPGA-Research-Manchester/zynq-ultrascale-readback-capture

  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the same task to Zynq UltraScale+ MPSoC with several noticeable differences.

  Language:Tcl13306

• chipsalliance/f4pga-v2x

  Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

  Language:Python10135412

• SymbiFlow/edalize

  An abstraction library for interfacing EDA tools

  Language:Python7513

• SymbiFlow/FPGA-Tool-Performance-Visualization-Library

  FTPVL is a library for simplifying the data collection and visualization process for Symbiflow development.

  Language:Python6393

• EliasVansteenkiste/EvaluationFramework

  Vivado scripts for the measuring the divide between academic and commercial FPGA CAD flows

  Language:VHDL3221

• khoapham/zynq_driver

  Language:C2103

• SymbiFlow/prjxray-experiments-archive-2017

  These are experiments which we conducted in 2017 as part of Project X-Ray.

  Language:Verilog21201

• byuccl/prjxray

  Documenting the Xilinx 7-series bit-stream format.

  Language:Python130