AAWO

Warsaw

Pinned Repositories

alfred-invert-SI
Calculate the inverse of a value with SI prefix, i.e.: from 50MHz (frequency) calculate 20ns (period)
Language:Python00
artiq
A leading-edge control system for quantum information experiments
Language:Python00
ddccontrol-db
DDC Control Monitor Database
Language:Shell00
FMC_ADC100M_10B_TDC_16cha_gw
ARTIQ gateware for FMC_ADC100M_10B_TDC_16cha
00
invoice-date-parser
(EN) Date parser for invoices - (PL) Parser dat z faktur
Language:Shell00
migen
A Python toolbox for building complex digital hardware
Language:Python00
misoc
A high performance and small footprint system-on-chip based on Migen
Language:Python00
modelsim-docker
Dockerfile for ModelSim Version 16 GUI
Language:Dockerfile00
verilog_inout_delay
Delayed bidirectional connection module
Language:Verilog00
VerilogDevEnv
Verilog Development Environment
Language:Verilog00

AAWO's Repositories

AAWO/alfred-invert-SI
Calculate the inverse of a value with SI prefix, i.e.: from 50MHz (frequency) calculate 20ns (period)
Language:Python00
AAWO/artiq
A leading-edge control system for quantum information experiments
Language:Python00
AAWO/ddccontrol-db
DDC Control Monitor Database
Language:Shell00
AAWO/FMC_ADC100M_10B_TDC_16cha_gw
ARTIQ gateware for FMC_ADC100M_10B_TDC_16cha
00
AAWO/invoice-date-parser
(EN) Date parser for invoices - (PL) Parser dat z faktur
Language:Shell00
AAWO/migen
A Python toolbox for building complex digital hardware
Language:Python00
AAWO/misoc
A high performance and small footprint system-on-chip based on Migen
Language:Python00
AAWO/modelsim-docker
Dockerfile for ModelSim Version 16 GUI
Language:Dockerfile00
AAWO/verilog_inout_delay
Delayed bidirectional connection module
Language:Verilog00
AAWO/VerilogDevEnv
Verilog Development Environment
Language:Verilog00
AAWO/xbar-plugins
Plugin repository for xbar (the BitBar reboot)