Adr-hyng/FPGA-Counters

This repo is for our final term project for Hardware Description Language using FPGA Board to explore real-time simulation using Verilog.

FPGA-Counters

This is the repo for our final term project for Hardware Description Language, which will be using Verilog code to perform low-level computations. Here we are using FPGA Development board which is the "Altera Cyclone IV ep4ce6e22c8n development board". IDK, if the board is cracked or what, but it outputs or performs gate-level inversely.

Note: Debouncing logic is implemented for presentation purposes, instead of continuously cycling when it is synthesized in the FPGA dev. board.