This project is for providing transparency and dynamic rebinding of the use of heterogeneous accelerators on edge micro data centers
Compile sycl code for multiple target backends with linker option to specify file offset of clang offload section
e.g. clang++ -fsycl -fsycl-targets=[backend list] main.cpp -Xlink [linker arg] (-Xlink [linker arg]) -o out.exe
[backends list] : comma seperated list
spir64_x86_64 for Intel CPU backend
spir64_gen for Intel GPU (ComputeCpp) backend
spir64_fpga for Intel FPGA backend(emulation or real device)
nvptx64 for NVIDIA PTX backend* (llvm should be configured *cuda enabled and compiled to use this target)
[linker arg] : argument of GNU linker 'ld'
--section-start <section_name>=<address>
<section_name> : __CLANG_OFFLOAD_BUNDLE__sycl-{target backend}
[address] should be greater than any other section's address
Write compiler script template OR Modify linker script
Intel LLVM-based projects (https://github.com/intel/llvm)
See sycl branch and DPC++ Documentation.
DPC++ is an open, cross-architecture language built upon the ISO C++ and Khronos SYCL* standards. DPC++ extends these standards with a number of extensions, which can be found in sycl/doc/extensions directory.
See openmp branch.
See LICENSE.txt for details.
See CONTRIBUTING.md for details.
*Other names and brands may be claimed as the property of others.