Static analyzer for standard an ultra circuits

[Rumata888]

A mechanism that treats the whole circuit before finalization (in case of ultra) as a graph with additional information and looks at the following properties:

1. How many independent subgraphs (real variables being vertices) there are
2. Whether there are any unexpected variables only present in 1 gate (apart from known cases this signals and underconstrained circuit)

Tasks

Beta Give feedback

1. Create Initial implementation of static analyzer with lookup, arithmetic, sorted, elliptic gates taken care of
2. Create PR patch for the discovered issue
3. Finalize and clean up PR with initial implementation and with AES and SHA256 tests
4. Create tests for blake
5. Extend mechanism to Auxiliary and Poseidon gates
6. Create tests for cycle group