BenBergman/lis3dh-rs

upstream master stability

jacobrosenthal opened this issue · 3 comments

I think the mcu gets reset in the middle of a transaction or something which puts the accel in an odd state.
It happens most? of the time when I upload a new image over hf2 or uf2.

If I pull the power it generally comes back up fine.

Of note Ive never seen it on debugger. So maybe debugger does a power cycle and clears it out. Or maybe its clearing the mcu's i2c stuff?

The only thing I can think it probably could have and would have happened before our refactor, but now that I have an is_data_ready im reading in a tight loop at the data rate of the accel, so its just 100% more likely to come across it now?

Ive tried implementing 'boot' and a delay but that doesnt help, because it isnt really a reset I dont think. I think it resets calibration registers... This chip just doesnt have a reset other than toggling the power I think. (which isnt connected on my board)

Which, off topic, means we dont need to bother implementing reset on startup, but maybe should instead write default values to all the ctrl regs on startup instead?

Ill see if I can spot something the atsamd hal to wiggle the i2c and rescue it.. other wise I might just have to document power cycles...

But keep your eyes open, and Ill keep trying to track down before we release.

Would it be worth trying to reproduce with an Arduino library and flashing with the same way as your rust code for the purposes of validating it is a hardware issue?

Its an adafruit board --- and I have 20 of them :)

Alright. Can confirm this was present in the older published versions as well, its just rearing its head I think because of the tight loop reading.

I have a pr to turn the hang into a panic in atsamd,
atsamd-rs/atsamd#239

but doesnt seem like doing a boot reset helps so theres nothing to do in this repo I dont think.