Deca Video Frame buffer example with your DDR3 controller
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Hi Brian and congratulations on your awesome work!!!!
This is not really an issue, but just as we are developing cores for Deca board we just need a way to implement your DDR3 controller to allow a video frame buffer for most of the cores at https://github.com/DECAfpga to output a proper HDMI video with standard resolution to make it compatible with the majority of monitors.
If you have the expertise to do that, we would love to see that example of use!!!
The Arcade cores would be a perfect target as they do not require anything else but the Deca and a Keyboard.
Thanks again.
Just take a look at the show 1080p demo and show GFX demo. The source code is well documented.
Within about a week, I will be adding v1.60 with a new show graphics output function which will properly allow 480p through 1080p switching, 1/2/4/8/16/32 bpp, multiple hardware window layers with alpha layer translucency, text/font tile mode (also 1/2/4/8/16/32 bpp with individual character mirror and flip, up to 16384 tiles, each with 4/8/16/32 X&Y dimensions) which uses the onboard FPGA blockram as font/tile memory, multiple palettes and individual integer X&Y scale controls for each layer, all controlable and addressable through all of the 16 DDR3 IO ports. Returned, you will be provided an H & V toggle signal for generating your own interrupt function for sync animations. (Yes, each layer can have individual palettes and different bpp color modes on each layer, though, multiple 1080p 32bit color layers un-zoomed 1x1 can outrun available DDR3 bandwidth.)
That sounds great Brian!
I hope that someone with more knowledge than me will be able to implement an upscaler in one of the available retro cores for Deca.
I'll be following your updates.
Thanks
What would be AWESOME is to get rid of SDRAM and run all Deca retro cores with purely DDR3.
Are you aware of any implementation of your controller in a retro core or similar ?
Sorry, I will not be doing anything else other than the core DDR3 and the multi-window VGA buffer generator. Everything else is up to you. (Or send my DDR3 page to those who developed those retro cores and nag them...)
My next step will be to upgrade my core to Lattice ECP5 series FPGAs. Their 45K cell 2mb core ram FPGA is only 15$ and their 85K cell 4mb core ram is only 32$ at Digikey roasting the price point of Altera/Intel & Xilinx. (With Lattice public domain tools, you can hack their 6.50$ 12K cell version into a respectable 25K cell version as the silicon is identical except for the FPGA ID code)
You've done a lot of work, so thanks for it.
Great tip about the Lattice one!