ChinnuReddySeelam

Pinned Repositories

100DaysRTL_Part1_HDL
Language:Verilog100
100_days_of_RTL_Part_2_Verification_Phase
50
Design-and-Verification-of-AMBA-APB-Protocol
20
24_Hr_Hackthon_Project
Language:Verilog10
ChinnuPortfolio.co.in
Language:HTML10
dESIGN-OF-8o85-4-BIT-MICROPROCESSOR-using-HDL
Language:Verilog10
Temperature-Monitoring-Forest-Fire-deduction-Alert-system
10
Verification-of-8-bit-RAM-and-Combinational-Adder-using-UVM
10
32Bit_Fast_Adder_Implementation
32Bit_Fast_Adder_Implementation
00
32BitFastAdders
Language:Verilog00

ChinnuReddySeelam's Repositories

ChinnuReddySeelam/FastMultipliers
ChinnuReddySeelam/DMA
Language:Verilog
ChinnuReddySeelam/32BitFastAdders
Language:Verilog
ChinnuReddySeelam/32Bit_Fast_Adder_Implementation
32Bit_Fast_Adder_Implementation
ChinnuReddySeelam/Base_RISC_V
Language:Verilog
ChinnuReddySeelam/CordicAlgorithm
ChinnuReddySeelam/24_Hr_Hackthon_Project
Language:Verilog1
ChinnuReddySeelam/RTL_Design_Of_RISC_32_I
Language:Verilog
ChinnuReddySeelam/100_days_of_RTL_Part_2_Verification_Phase
5
ChinnuReddySeelam/Portfolio
ChinnuReddySeelam/100DaysRTL_Part1_HDL
Language:Verilog10
ChinnuReddySeelam/AlarmProject
Language:Verilog
ChinnuReddySeelam/JTAG_Implementation
Language:Verilog
ChinnuReddySeelam/Design-and-Verification-of-AMBA-APB-Protocol
2
ChinnuReddySeelam/Verification-of-8-bit-RAM-and-Combinational-Adder-using-UVM
1
ChinnuReddySeelam/FIFO-and-Digital-clock-design-and-verification-using-system-verilog
ChinnuReddySeelam/EVM-AES
ChinnuReddySeelam/dESIGN-OF-8o85-4-BIT-MICROPROCESSOR-using-HDL
Language:Verilog1
ChinnuReddySeelam/Temperature-Monitoring-Forest-Fire-deduction-Alert-system
1
ChinnuReddySeelam/ChinnuPortfolio.co.in
Language:HTML1
ChinnuReddySeelam/Portfolio.com
Language:HTML