RISC-V is an open source instruction set architecture. Every processor are in simplistic view are set of logic elements connected together. To accomplish high level tasks such as video editting, browsing on the internet or simulating complicated mechanical designs, we would need a a lot easier interface to be able to do anything. Graphical user interface is a simple interface to the code, code is a simple interface to the machine. Machine can only understand binary information which means the code must be transformed to the binary data. That data must be in such order that desired task can be accomplished by the logic gates. Instruction set architectures define those binaries for a specific architectures. It is not the only instruction set but the only prevailed full open source instruction set. The binaries genereted according to those instruction sets can opperate on any RISC-V processor. It is also possible to extend the architecture by your own designs. Those extensions may not opperate on every hardware depening on the compiler configurations. This repository represent a processor that have minumum requirements of a RISC-V arcitechture. The purpose of this design is to share a simple to understand example of the most basic processor design.
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This repository is a RISC-V core project implemented with hardware description language verilog which means that if you have an fpga board available you can compile my code with the rigth software for your specific chip. Although I would recomand you to test my code with open source verifaction tests such as COCOTB if you are going to use in real life applications. Doing the complete verification is one of my plans for the future as well as extending the RISC-V instruction set also adding branch prediction, pipline and cache memory.
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+Easy to understand RISCV processor
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+Intuative verification method with assembly code (as it turns out it is impracticle method for real life applications and verification is not a simple for even basic cores)
This module does not contain:
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-No cache memory
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-No pipline structure
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-No branch prediction
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-Not fully verified