Review Melodica area

[nirajnsharma]

The melodica is 5X the number of gates of an equivalent FPU. This needs to be reviewed and understood.

[nirajnsharma]

Since the melodica is not being used in a pipelined manner here, all FIFOs can be reduced to single entry FIFOs.

[nirajnsharma]

@farhadmerchant I have made some modifications to the Melodica source specifically around the size of the pipeline FIFOs used through the design. When used with Clarinet, the core cannot be used in a pipelined fashion due to the limitations in the Clarinet pipeline. I have therefore reduced the buffering in these FIFOs which should close to halve the number of FFs.

Please do a --recursive pull of Clarinet and rerun synthesis on the generated Verilog RTL.

[nirajnsharma]

Refactored extracter, normalizer, and Mac.