Pinned Repositories
Layered_testbench_memory
SV_assertions
uvm-yapp-router-verification-yapp-uvc
UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)
Advanced-Audio-Signal-Processing-and-Noise-Reduction-Unleashing-Sonic-Synergy-
This project explores techniques for enhancing audio quality and reducing noise using MATLAB. Key features include spectral analysis, adaptive noise reduction using LMS, various filtering methods, and voice activity detection (VAD). A user-friendly GUI allows for interactive control of playback levels, showcasing practical audio processing applicat
AeroPathfinder
This project integrates Dijkstra's algorithm into a Flight Management System (FMS) to optimize route planning, aiming for a 20% reduction in flight durations and a 15% decrease in fuel consumption. It enhances operational efficiency, while providing an educational tool for Data Structures and Algorithms.
Emotion-Recognition-using-FER-and-CNN
This project develops a robust emotion recognition system that identifies human emotions from facial expressions. Utilizing the FER+ dataset and Convolutional Neural Networks (CNN), it achieves 83.52% validation accuracy through effective data augmentation and pre-processing technique, showing advanced deep learning in emotion detection
fifo_layered_testbench
Layered SystemVerilog testbench for verifying a parameterized Synchronous FIFO. Includes directed and constrained-random tests, functional coverage, assertions, and scoreboard-based checking.
NexusChat
Multi-client Chat Application using Socket Programming in Python with Tkinter and SQLite. Allows users to register/login, exchange text messages, and share images. Features a GUI interface, password encryption, and performance analysis. Includes server-side and client-side implementations.
uvm-yapp-router-verification-Environment
A complete UVM-based verification environment for validating YAPP Router functionality using SystemVerilog and Cadence Xcelium, featuring advanced sequences, virtual interfaces, and coverage analysis.
uvm_fifo_tb
Hampton-bit's Repositories
Hampton-bit/Layered_testbench_memory
Hampton-bit/SV_assertions
Hampton-bit/uvm-yapp-router-verification-yapp-uvc
UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)
Hampton-bit/Advanced-Audio-Signal-Processing-and-Noise-Reduction-Unleashing-Sonic-Synergy-
This project explores techniques for enhancing audio quality and reducing noise using MATLAB. Key features include spectral analysis, adaptive noise reduction using LMS, various filtering methods, and voice activity detection (VAD). A user-friendly GUI allows for interactive control of playback levels, showcasing practical audio processing applicat
Hampton-bit/AeroPathfinder
This project integrates Dijkstra's algorithm into a Flight Management System (FMS) to optimize route planning, aiming for a 20% reduction in flight durations and a 15% decrease in fuel consumption. It enhances operational efficiency, while providing an educational tool for Data Structures and Algorithms.
Hampton-bit/Emotion-Recognition-using-FER-and-CNN
This project develops a robust emotion recognition system that identifies human emotions from facial expressions. Utilizing the FER+ dataset and Convolutional Neural Networks (CNN), it achieves 83.52% validation accuracy through effective data augmentation and pre-processing technique, showing advanced deep learning in emotion detection
Hampton-bit/fifo_layered_testbench
Layered SystemVerilog testbench for verifying a parameterized Synchronous FIFO. Includes directed and constrained-random tests, functional coverage, assertions, and scoreboard-based checking.
Hampton-bit/NexusChat
Multi-client Chat Application using Socket Programming in Python with Tkinter and SQLite. Allows users to register/login, exchange text messages, and share images. Features a GUI interface, password encryption, and performance analysis. Includes server-side and client-side implementations.
Hampton-bit/uvm-yapp-router-verification-Environment
A complete UVM-based verification environment for validating YAPP Router functionality using SystemVerilog and Cadence Xcelium, featuring advanced sequences, virtual interfaces, and coverage analysis.
Hampton-bit/uvm_fifo_tb
Hampton-bit/OpenCores-SPI-Interface-UVM-Verification
Hampton-bit/UVM-YAPP-Router-Verification
UVM testbench demonstrating multi-UVC integration for YAPP router verification with HBUS register interface, channel protocol monitoring, and comprehensive SystemVerilog verification methodologies.
Hampton-bit/yapp-router-tlm-uvm