Informaticore/SuperPower

Review Actions

Opened this issue · 1 comments

General

  • Use DNP for unpopulated parts
  • Create consisten page settings over all sheets

Random

  • fix footprints of capacitors C707&C717, C709&C71, C713&C718. The footprint is identical but different in the pads
  • redraw U701 and U702 symbol showing 1213 and 78
  • make units consistent either 0.1uF or 100nF. Let us go with uF
  • For R20 & R21, change the values to reduce the unique part count by 1. The 22k can be changed to 10k, and the 47 can be something around 21.3k (=47k/22k)
  • Mark R12 as DNP and leave Q4A (Default setup)
  • Make R1 470 Ohm
  • Change values of R701, R703, R706, and R707 to match the desired voltage but also fit other resistor values like 100k
  • Add a switch to J601 (ext wakeup) but DNP as addition to wake up on press or external event, SKRKAEE020.
  • Remove 0805 and 0603 text comments from the schematic and choose the footprint
  • Remove VIN from MCU sheet including the tracks because it is unused
  • Mark screw-terminal on charger IO sheet as DNP and remove JST connector (misplaced)
  • Hide PWR_FLAG label
  • Change R1, R19, R22 to 470 Ohm
  • Hide value fields of JP1 and JP2
  • Remove the labels CHREN, CHR0 and CHR1 and place TestPoints for them
  • connect 5V_EN and 3v3_EN also to the pinheader
  • Rename Labels: Vin on charger-io sheet to 3v3_RTC
  • discuss ORing circuity (@2010019970909 and Seth)

Charger sheet

  • Move images from the Charger sheet into a ReadTheDocs Page, only keep formulas as text
  • finish the SMBALTERT LED circuit with LED and resistor value
  • Attach SMBALERT track to the pin 32 of the MCU
  • Dump R4 and R5 and use 3-way-solder-jumper for JP1 and JP2 with a cutting track
  • Max cell count is LTC4162L, we should change the posibilities of the board to match that. Remove JP2 and R5
  • Unify R11 and R7
  • Replace NTC Resistor with a 10k value one (as default)

last step to not loose references from review:

  • re-anotate the whole project for the sake of consistent designators

Here is a LTSpice simulation for the ORing.

ORing.zip