JeffDeCola/my-masters-thesis

A High-Level Design Framework Illustrating Technology Migration.

MY MASTERS THESIS

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A HIGH-LEVEL DESIGN FRAMEWORK ILLUSTRATING TECHNOLOGY MIGRATION

BY Jeffry A. DeCola

Submitted to the University of New Hampshire in Partial Fulfillment of the Requirements for the Degree of Master of Science in Electrical Engineering

Copies of my thesis are located at the UNH Diamond Library and the UNH Engineering, Math & CS Library

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ABSTRACT

This thesis presents a comprehensive high-level design framework which embodies the multiplicity of system models (from physical to behavioral) and microsystem technologies (from standard parts to multichip modules (MCMs)) as well as the interrelations between them (vertical and horizontal design methodologies). This framework is used as a guide to understand, view and analyze all areas of complex system development, especially technology migration (e.g. integrating logic using field programmable gate arrays (FPGAs) instead of standard parts). The description tool VHDL provides a means to accomplish technology migration as demonstrated in two practical applications: laboratory experiments of a NASA Host Interface Serial Controller (HISC) and an 8-bit microprocessor design, both functionally implemented using an FPGA technology.

TABLE OF CONTENTS

• TITLE AND COPYRIGHT
• EXAMINED AND APPROVED
• DEDICATION
• ACKNOWLEDGMENTS
• PREFACE
• LIST OF FIGURES
• LIST OF TABLES
• TRADEMARKS
• ABSTRACT

1 INTRODUCTION

2 DESIGN DOMAIN, DESIGN FRAMEWORK AND TECHNOLOGY MIGRATION IN MICROSYSTEM DEVELOPMENT

• 2.1 Design Domain
  • 2.1.1 Schematic Capture View of the Design Domain
  • 2.1.2 VHDL View of the Design Domain
• 2.2 Design Framework
• 2.3 Technology Migration (Horizontal Design Methodology)
  • 2.3.1 Technology Migration using Schematic Capture
  • 2.3.2 Technology Migration using VHDL
• 2.4 Summary

3 SYSTEM MODELS, DESCRIPTION TOOLS AND SIMULATION

• 3.1 Five Levels of Abstraction
• 3.2 Domains and Classes of Abstractions
  • 3.2.1 Domains of the Abstraction Levels
  • 3.2.2 Classes of the Abstraction Levels
• 3.3 Schematic Capture and Simulation
• 3.4 Hardware Description Languages and Simulation
  • 3.4.1 High-Level HDL Applications and Benefits
  • 3.4.2 Limitations - Industry View of an HDL
  • 3.4.3 The Language Tree
  • 3.4.4 Classification of Common Languages
• 3.5 Multi-Level Description Environment and Multi-Level Simulation
• 3.6 VHDL
  • 3.6.1 Benefits and Limitations of VHDL
  • 3.6.2 Four Types of VHDL Models
  • 3.6.3 VHDL Library Design Units

4 DESIGN SYNTHESIS

• 4.1 Synthesis
• 4.2 Types of Synthesis
• 4.3 Synthesis for Technology Migration
• 4.4 Synthesis System
  • 4.4.1 Design Automation
  • 4.4.2 Benefits of High-Level Synthesis Systems
  • 4.4.3 Limitations of High-Level Synthesis Systems
• 4.5 Modeling for the Synthesis System
  • 4.5.1 Modeling for the Synthesis System using VHDL
  • 4.5.2 Modeling for the Target Technology using VHDL

5 OVERVIEW OF MICROSYSTEM TECHNOLOGIES

• 5.1 Technology Breakdown
• 5.2 Standard Parts and PLDs
• 5.3 All-Mask ASICs
• 5.4 Gate Arrays and FPGAs
  • 5.4.1 Gate Arrays
  • 5.4.2 FPGA Architectures and Programming
• 5.5 Multichip Modules (MCMs)
  • 5.5.1 A New Technology
  • 5.5.2 Design Issues
  • 5.5.3 Multichip Module Assemblies
• 5.6 Selecting a Technological Device
  • 5.6.1 The Logic Integration Tool (LIT)
  • 5.6.2 Software Aided Selection Issues

6 LOW-LEVEL VERTICAL DESIGN METHODOLOGY

• 6.1 Low-Level Design Methodology
  • 6.1.1 Bottom-Up Modeling
  • 6.1.2 General Low-Level EDA Environment
  • 6.1.3 General Low-Level Steps
• 6.2 Evaluation of Low-Level Vertical Design Methodology
  • 6.2.1 Goals of a Design Methodology
  • 6.2.1 Evaluation

7 HIGH-LEVEL HORIZONTAL DESIGN METHODOLOGY (TECHNOLOGY MIGRATION)

• 7.1 High-Level Design Methodology (Technology Migration)
  • 7.1.1 Top-Down Modeling
  • 7.1.2 General High-Level EDA Environment
  • 7.1.3 General High-Level EDA Environment
• 7.2 Evaluation of Technology Migration

8 CONCLUSIONS

REFERENCES

• I. General Related Documentation
• II. Alternative System Concepts and CAD Language Systems, Inc. Related Documentation
• III. Mentor Graphics Related Documentation
• IV. Texas Instruments and Actel Related Documentation
• V. Viewlogic Related Documentation
• VI. Xilinx Related Documentation
• VII. Other Related Documentation

GLOSSARY

• I. General Acronyms and Technical Terms
• II. CAE Environment Acronyms and Technical Terms

APPENDICES

• APPENDIX A
  • HARDWARE AND SOFTWARE USED
    • I. HARDWARE USED
    • II. SOFTWARE USED
• APPENDIX B
  • HOST INTERFACE SERIAL CONTROLLER (HISC) (CORRELATOR CONTROLLER) ARCHITECTURE
    • I. NASA CORRELATOR
    • II. CORRELATOR PROCESSOR ARCHITECTURE
    • III. HOST INTERFACE SERIAL CONTROLLER
• APPENDIX C
  • LABORATORY 1: SOFTWARE AIDED DEVICE SELECTION WITH THE TI LOGIC INTEGRATION TOOL (LIT)
• APPENDIX D
  • LABORATORY 2A: SCHEMATIC CAPTURE WITH VIEWLOGIC'S VIEWDRAW
• APPENDIX E
  • LABORATORY 3A: SCHEMATIC CAPTURE HIERARCHICAL DESIGN WITH VIEWLOGIC'S VIEWDRAW
• APPENDIX F
  • LABORATORY 4A: SCHEMATIC CAPTURE SIMULATION WITH VIEWLOGIC'S VIEWSIM
• APPENDIX G
  • LABORATORY 5A: PROGRAMMING A TI TPC12 FPGA WITH TI-ALS TOOLS
• APPENDIX H
  • LABORATORY 2B: VHDL MODEL AND LOGIC SYNTHESIS WITH VIEWLOGIC'S VHDL TOOLS
• APPENDIX I
  • LABORATORY 3B: VHDL HIERARCHICAL DESIGN WI1H VIEWLOGIC'S TOOLS
• APPENDIX J
  • LABORATORY 4B: VHDL SIMULATION WI1H VIEWLOGIC'S VIEWSIM
• APPENDIX K
  • LABORATORY 5B: PROGRAMMING A TI TPC12 FPGA WI1H TI-ALS TOOLS
• APPENDIX L
  • PROGRAMABLE 8-BIT MICROPROCESSOR
    • I. TOP-LEVELS OF THE MICROPROCESSOR
    • II. GENERIC VHDL TEST GENERATION TEMPLATE
    • III. STRUCTURAL VHDL DESCRIPTION OF THE 8-BIT MICROPROCESSOR