Annular widths of vias are too small
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I quickly looked over the PCB - noting what I found in case it's relevant
Here your annular rings are tiny. See minimum size as per JLCPCB below
Same with the LEDs - you should be able to get away with the actual minimum required annular ring (0.13mm).
Happens all over the board. I didn´t take a look at the original Sofle - the issue might also be present there - but violating minimum annular width might lead to more production failures. When you order like 5 boards, you will get 5 functioning boards, because they often overproduce and test every board at small scales - at least for JLCPCB - but it's not good practice to go for such small tolerances.
EDIT: Just noticed - the LED mount is part of the Cherry_MX_DS_Hotswap_miniE_1U_v3.03 footprint - so, not directly related to your routing. But I would recommend making your default Via size 0.3mm unless specifically needed smaller:
The vias around the Pico footprint are 0.2/0.4mm - I´d go for a standard size of 0.3/0.6mm - it looks like there's more than enough space for it.
Thanks for taking a look!
I put these footprints together from a few sources. I got the combo schematic symbol from the Sofle Choc, and then i adapted the LED footprints from one of Zerf9's Chunky pcbs. As far as I know, a finalized version of Chunky hasn't been released yet, so I don't have 100% confidence in putting vias between the LED pads.
I've successfully produced three generations of this board though - so my confidence is high in the drill hole/annular specs work with JLC. However - you bring up a really good point - building for the minimum specs of one manufacturer is limiting. The target audience for this board is the enthusiast/hand builder, so that's another strong argument for 'bullet proofing' the solder pads.
I'm going to refactor the LED footprint to add some more breathing room, as well as split the footprints for the LED's & the switches into separate footprints for PCBA.
@uberrice I tweaked the LED footprints and annular ring standards. I decided not to split the LED/Switch footprints. After giving it some thought, I don't think I'm going to spend the time to rewire the board to optimize for PCBA. (Other than the level-shifters & diodes -which are already setup for PCBA).
I did put in an order today for v3.4.4 boards. If you want to place an order for those, i have a high degree of confidence based on the viability of the last 3 iterations. If you want to wait a few weeks, I can confirm that it's 100% working.
Over the next few weeks, i'll focus on cleaning up my documentation and getting the QMK commit ready to go.
@JellyTitan I'm fairly sure that the pads will most probably work out if you're just ordering 5 boards and JLCPCB doesn't ask you about it. They'll just make the board, and if one doesn't work, they'll throw it away and only send you the ones that do work.
As these boards are usually made for the enthusiast who will order 5 boards for themselves, and no more, this is not an issue (but this is also probably why all the store-sold version of boards have their own 'tweaked version' :) )
As in my country, Fedex, which is at my door within 1 week of me ordering, is around the same price as the cheap shipping, I think I'll wait til you had time to test the board!
JLC hit me with the 'too many slots' fee. I've fixed that before by replacing the LED hole "edge cuts" with through holes in the footprints. I'm going to try to cancel the order and make that fix, since it increases the cost of small batch orders by ~50%. (Plus it's been an intermittent problem on other Sofle generations).
I think I'm unclear on the annular minimums - for the board vias around the pico, i've bumped it up to 0.3/0.6mm like you recommend, and on the LED's I tweaked it to be 0.3/0.5mm. (There's wasn't enough room between the LED pads to go up to .3/.6 without some edge clearance violations. Looking at the docs, I think .3/.5 puts it well over the minimum specs:
Am I interpreting those specs correctly? It looks like there's a few conflicting specs for annular ring minimums listed on that page?
This spec would seem to imply hole diameter + .3 for the annular min:
From this forum thread, it looks like the difference in specs stems from a meaningful distinction between via & PTH:
https://3d.jlcpcb.com/help/answers/detail/110-minimum-via-size-vs.-minimum-annular-ring-size
Since the LED vias are made using a footprint, they are semantically a PTH and not a via. . . but I don't know what the distinction would be from a manufacturing perspective? Any insight on that? Maybe I'm splitting hairs and need to rebuild that footprint?
PTH is for components that actually go through it - it's specified that way because below that width, jlcpcb treats any hole as a via - which means the hole might be obstructed by copper or the surface treatment. This isn't a problem for vias, as you don't need to push things through them. So, any hole that doesn't need anything to go through it, you can treat as a via.
As for the "conflicting information". A via needs to be a minimum of 0.4mm wide - that is the width of the copper 'circle'. Additionally, the annular ring - the length between the edge of the hole and the edge of the pad - needs to be 0.13mm wide. JLC seems to have a minimum hole size of 0.2 - with a tolerance of +0.13-0.08. So, if you make your hole 0.2 and the via 0.4, you have an annular ring of 0.1 - too small, theoretically. But, looking at how they state it, going 0.2/0.4 is fine. This limitation is simply a tolerance thing. Top and bottom have an alignment tolerance - the layers aren't going to be EXACTLY on top of each other, and the drill also has a tolerance - it won't be EXACTLY in the correct place. In order to make this more easily understandable, they just give you minimum size constraints with those tolerances in manufacturing in mind.
Keep in mind these tolerances vary from manufacturer to manufacturer, and product to product. For example, a 4 layer board on JLC allows for way more intricate designs. But, generally, the more intricate, the more expensive.
TLDR - for small batch production, 0.2/0.4 vias should be fine. If you can find the space, make it 0.2/0.46 to stay exactly within JLCs capabilities.
Interesting! Thank you for the manufacturing insight, I've never produced more than a 5 board batch. Treating TH as a via completely makes sense. Considering the potential for defects that you mentioned above, I felt it was worth the time to refactor for bigger vias. I overhauled the LED footprint and updated the traces for a consistent .3/.6. That was a major adjustment, so my confidence level is medium. I placed a JLC order yesterday, so I should be able to validate in a few weeks when it arrives.
I took a look at what some of the other popular boards are doing. It looks like the Sofle family are the odd ones with with 2/4. (Thats doubly odd, considering the lineage is Helix->Lily58->Corne->Sofle)
| Board | Hole Width (mm) | Via dia (mm) |
|---|---|---|
| Sofle V1 | .3 | .4 |
| Sofle V2 | .3 | .4 |
| Sofle RGB | .3 | .4 |
| Sofle Choc | .3 | .4 |
| Corne Classic | .4 | .6 |
| Corne Choc | .4 | .6 |
| Helix | .4 | .6 |
| Lily 58 | .4 | .6 |
| Stront | .4 | .8 |
| Piantor | .3 | .6 |
| Chunky | .3 | .6 |
Took a look, looking good! I didn't get why the original footprint even was that constrained for space, given that it's within the courtyard of a switch anyways - no other component is going to be there.
Only minor thing I'd change:
While minor, this springs out to me as a site that might cause an acid trap.
I'd recommend to have it go with 45 degree angles rather than smooth out of the pad - or at least have the trace exit the pad at a 90 degree angle.
In other places, like below, it's not much of a problem as you have the 'teardropping' enabled, which makes it almost 90deg.
Looks like you've already somewhat redone the routes - did that get rid of the extra slot fee?
As I was already placing a rather substantial order on Aliexpress, I decided to order the parts for the keyboard already, so I just need the pcb.
Noted one bug just looking over it quickly:
Routing a GND net if you have a polygon is bad practice ;) not like it'd change anything here, but you are creating a (minor) ground loop.
I'll give the board another review in the evening and order it myself after. Worst case, I'm out a few bucks :)
Thanks for the review! I tweaked the LED footprint for the acid trap & pulled the unnecessary GND routing - thank you for the best practice tips. (I've no formal training, so that sort of thing is super helpful!) I pushed up the changes:
Gerbers/production_ready/Sofle_Pico_v3.5.1_11-14-23.zip
If you find any other improvements, please let me know and I'll get them in here.
Forgot to mention - it looks like changing the LED holes from edge cuts to overlapping holes fixed the 'too many slots' fee. JLC's application of that fee has been really inconsistent - so i'm not sure the problem was truly fixed. I'm curious if they will charge for your order. I did request component placement review, and they did correct some diode placement/orientation. I'm not too concerned though - i've never had the component placement work correctly without reviews.
Before:
After:
I outlined my changes in uberrice#1 . I found no breaking issues, however the ground/vcc layer connection was rather iffy at a lot of parts, along with too little of a pullback around the edge of the board (during milling, because of the 0.2mm milling tolerance, it can happen that a speck of copper gets caught between top and bottom plane, causing a short between VCC and GND. That's not good.
I ended up rerouting some nets as well, all described in the issue. I'll order this version and tell you how it works out.
Wow! That was some nice work! There's ton's of concepts there that I'm unfamiliar with. It'll take me a few days to go through and unpick/understand what's really happening there.
I'd like to merge those changes into the main branch - but I'm also greedy for the learning opportunity, so it'll be awhile.
It looks like the logo is breaking due to missing fonts. I'll convert that into a footprint.
Bit of a side note here - I'm not 100% certain that the level shifter is required - but I haven't tried it.
I added the level shifter bypass because someone mentioned that SK6812MINI-E would work fine with the RP2040, and the first in the circuit would act as a level shifter.
I tried it with the SK6812's, and the right hand board overheated and shutdown. (I would have preferred to use those because they are more common in keyboards).
I haven't tried bypassing the level shifter with the lower amperage SK6803's.
My electricity math is bad, so I was just gonna try it.
Thoughts?
First off: Review went through, they hit me with an 'others' fee of like 7 bucks ;) so I'm guessing whether they charge the slot fee or not is just related to how the engineer checking the board feels.
I only have reviewed the routing this time, not the logic. And as you say, yes, theoretically, the SK6812MINI-E wouldn't require a level shifter. According to the data sheet, they're compatible with logic voltage from 0.5-5.5 V
However, I am not sure what exactly they mean with 'signal input flip threshold'. 0.7*5 would be 3.5, which would be a bit above the pico's 3.3V. Anyways, it's good you have a level shifter that you COULD put in there - I'll try it without first.
It's likely the problem was more to do with the layout - the LEDs use power between the VCC and GND pins, mostly, and while your board had connections between all the VCC and GND pins, in some spots, the connections got awfully crowded. Heck, if you put the LEDs at 100% brightness, you'd have like 6W of LED power in one half of the board (going by '0.2W LED'), which goes WAY over USB spec! However, the same is true for the 6803.
You basically had the power for half the board run along the left side here:
While that should have been okay (you had almost a millimeter of 'trace' there) - you also had the 0.2mm tolerance, leaving you with 0.8mm.
Just as an example, the path of VCC for the LED on SW1:
And then to get back to ground:
I'm almost certain that might have lead to your overheating issue, and not the level shifter 'missing'. Well, we will see when I get my revision ;) I have also ordered SK6803's by the way.
What I think really needs to be done anyways is to somewhat limit the max power of the LEDs in Software - say, 40?50? % of their theoretical '100%' should be more than plenty, if not even lower.
@uberrice Since JLC charged for the drill-hole based LEDs, I'd like to reverted LED footprints back to the square edge-cuts. When assembling the LEDs - were the extra long holes helpful with tweezer placement?
@JellyTitan I basically just dropped them in there and put the tweezers on top to scoot them around, they basically should more or less 'self-align'. If anything, the holes were a bit big, the LEDs were almost able to 'slide between the pads'.
But I don't know how much tighter you can go with tolerances - 0.2mm or whatever it was is already quite large of a tolerance for those holes.