Pinned Repositories
Around-The-Mediterranean
FEA-on-FPGA
Using FPGA parellel computing to accelerate the FEA
FPGA-AES-encryptor
AES processor impelmented by Verilog. This processor can run at the frequency of 100MHz and take 10 cycles to encrypt an 128-bit plain text.The processor uses several simple commands and state bits to input, encrypt and output the data.
KevinLikesDringCoffe.github.io
MIPS32-pipelined-processor
a MIPS32 pipelined processor impelmented by Verilog HDL
Start-to-build-a-RISC-V-superscalar-processor
从零开始写一个基于RV32指令集的超标量处理器
Stencil-computation-on-FPGA
A simple stencil computation implemented by HLS
tt_fpga
Vitis_Libraries
Vitis Libraries
rapidstream-tapa
RapidStream-TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
KevinLikesDringCoffe's Repositories
KevinLikesDringCoffe/MIPS32-pipelined-processor
a MIPS32 pipelined processor impelmented by Verilog HDL
KevinLikesDringCoffe/FPGA-AES-encryptor
AES processor impelmented by Verilog. This processor can run at the frequency of 100MHz and take 10 cycles to encrypt an 128-bit plain text.The processor uses several simple commands and state bits to input, encrypt and output the data.
KevinLikesDringCoffe/Stencil-computation-on-FPGA
A simple stencil computation implemented by HLS
KevinLikesDringCoffe/Around-The-Mediterranean
KevinLikesDringCoffe/FEA-on-FPGA
Using FPGA parellel computing to accelerate the FEA
KevinLikesDringCoffe/KevinLikesDringCoffe.github.io
KevinLikesDringCoffe/Start-to-build-a-RISC-V-superscalar-processor
从零开始写一个基于RV32指令集的超标量处理器
KevinLikesDringCoffe/tt_fpga
KevinLikesDringCoffe/Vitis_Libraries
Vitis Libraries