How to control TCP0 and TCP1 alt modes from MCU
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I would like to use the TCP0 and TCP1 as Type-C with alt-mode. Diagram of what I am trying to do:
From what I can tell, these will require a PD controller. The full carrier board schematic uses a IT8851:
However I am unable to acquire an IT8851. I will use an MCU and control power delivery from that.
From what I can tell in the N100 datasheet, 26.1.1 states the following:
SMLink1 is used to communicate with USB-C* PD Controller on the platform to
configure different modes such as USB, Display Port, Thunderbolt*, etc. When used
for Integrated USB-C purposes, a soft strap must be set to indicate that integrated
USB-C ports from CPU are being used.
26.2 (yes wrong image, see comments below for right one)
This matches with what I see in the schematic for pins 3, 4 and 5. The datasheet also mentions a second I2C port (I2C2 on the module), something with retimers.
Although beyond what the datasheet states, there is nothing describing what messages get sent to and from the PD controller.
Regarding the I2C/Smbus interface, is this defined by the SoC or defined by the BIOS? Is LattePanda able to describe the interface to configure the USB-C port mode and muxing in TCP0 and TCP1 over smbus (what messages, layout of each message)? How many I2C interfaces do I need to use for this (1 or 2)?
I tried to see if coreboot had anything to reference on this. I could not find anything.
The previously linked datasheet is for a 600-series PCH. The Intel N100 Datasheet lists the pinstrap as follows
The previously linked datasheet is for a 600-series PCH. The Intel N100 Datasheet lists the pinstrap as follows
Yes I forgot to update the original image for the pin strap. Shouldn't change the question still.
I've discussed this a bit on the Discord, but posting here for reference. CrOS EC does have code to talk to the PD mux on the N100:
https://github.com/coreboot/chrome-ec/blob/main/zephyr/include/drivers/intel_altmode.h
https://github.com/coreboot/chrome-ec/blob/main/zephyr/drivers/usbc/intel_altmode.c
https://github.com/coreboot/chrome-ec/blob/main/zephyr/subsys/pd_controller/pd_task_intel_altmode.c
These describe the registers which you use to talk to the PD Mux over Type-C.
I also took a logic analyzer to the full carrier board. I tested with a USB-C to Displayport cable and a USB-C to HDMI + USB hub. Attached are pulseview captures (don't forget the second file for the labels).
LPMu_SMLink1_USBC_Aug04_2024.zip
The capture does show the INTEL_ALTMODE_REG_DATA_CONTROL and INTEL_ALTMODE_REG_DATA_STATUS addresses are used.
This capture only was performed on the TCP1 port since that is what the full carrier has connected for USB-C. I suspect the address written to the registers, 0x38 for TCP1, states which port to control?
