/Design-and-Verification-of-a-PCIe-Packet-Detector

Digital Design of a PICe packet detector FSM that detects whether the packet is a good or pad.

Primary LanguageSystemVerilog

Design-and-Verification-of-a-PCIe-Packet-Detector

Digital Design of a PICe packet detector FSM that detects the type of a 20-byte packet.