Hang after printing "NOTICE: Cold boot"
Opened this issue · 5 comments
I just did a fresh checkout of the 17.10 branches and flashed the flash-image.bin to SPI ROM on MACCHIATObin board, and am seeing this hang:
BootROM - 2.03
Starting CP-1 IOROM 1.07
Booting from SPI NOR flash 1 (0x32)
Found valid image at boot postion 0x000
lNOTICE: Starting binary extension
NOTICE: SVC: SW Revision 0x0. SVC is not supported
mv_ddr: mv_ddr-armada-17.10.5-gf537e1d (May 08 2018 - 09:54:23)
mv_ddr: completed successfully
NOTICE: Cold boot
I suspect it's related to compiling with GCC 7.3.0. Will try with GCC 5.4.0
Yes, it boots to U-Boot CLI just fine with GCC 5.4.0. The issue must be with GCC 7.x...
I tested the entire 17.10 release using Linaro GCC toolchain release
gcc-linaro-7.2.1-2017.11-x86_64_aarch64-linux-gnu
Everything looks OK.
Have you created your own cross-toolchain out of sources?
BootROM - 2.03
Starting CP-1 IOROM 1.07
Booting from SPI NOR flash 1 (0x32)
Found valid image at boot postion 0x000
lNOTICE: Starting binary extension
NOTICE: SVC: SW Revision 0x0. SVC is not supported
mv_ddr: mv_ddr-armada-17.10.5-gf537e1d (May 10 2018 - 02:49:59 PM)
mv_ddr: completed successfully
NOTICE: Cold boot
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v1.3(release):armada-17.10.8:34247e0
NOTICE: BL1: Built : 14:50:05, May 10 2018
NOTICE: BL1: Booting BL2
lNOTICE: BL2: v1.3(release):armada-17.10.8:34247e0
NOTICE: BL2: Built : 14:50:07, May 10 2018
BL2: Initiating SCP_BL2 transfer to SCP
NOTICE: SCP_BL2 contains 2 concatenated images
NOTICE: Load image to CP1 MSS
NOTICE: Loading MSS image from address 0x4023020 Size 0x1344 to MSS at 0xf4280000
NOTICE: Done
NOTICE: Load image to AP MSS
NOTICE: Loading MSS image from address 0x4024364 Size 0x1f20 to MSS at 0xf0580000
N
FreeRTOS 7.3.0 - Marvell cm3 - A8K release devel-18.04.0
OTICE: Done
NOTICE: SCP Image doesn't contain PM firmware
WARNING: Failed to obtain reference to image id=4 (-2)
WARNING: Failed to load BL32 (-2)
NOTICE: BL1: Booting BL31
lNOTICE: MSS PM is not supported in this build
NOTICE: BL31: v1.3(release):armada-17.10.8:34247e0
NOTICE: BL31: Built : 14:50:10, May 10 2018
l
U-Boot 2017.03-armada-17.10.3-00526-g75ce169 (May 10 2018 - 14:49:10 +0300)
Model: MACCHIATOBin-8040
SoC: Armada8040-A1; AP806-A1; 2x CP110-A1
Clock: CPU 2000 [MHz]
DDR 1050 [MHz]
FABRIC 1050 [MHz]
MSS 200 [MHz]
DRAM: 4 GiB
U-Boot DT blob at : 000000007f70bab8
EEPROM configuration pattern not detected.
Comphy chip #0:
Comphy-0: PEX0
Comphy-1: PEX0
Comphy-2: PEX0
Comphy-3: PEX0
Comphy-4: SFI
Comphy-5: SATA1
Comphy chip #1:
Comphy-0: SGMII1 1.25 Gbps
Comphy-1: SATA0
Comphy-2: USB3_HOST0
Comphy-3: SATA1
Comphy-4: SFI
Comphy-5: SGMII2 3.125 Gbps
UTMI PHY 0 initialized to USB Host0
SATA link 0 timeout.
SATA link 1 timeout.
AHCI 0001.0000 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
flags: 64bit ncq led only pmp fbss pio slum part sxs
SATA link 0 timeout.
SATA link 1 timeout.
AHCI 0001.0000 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
flags: 64bit ncq led only pmp fbss pio slum part sxs
PCIE-0: Link down
MMC: sdhci@6e0000: 0, sdhci@780000: 1
SF: Detected w25q32bv with page size 256 Bytes, erase size 4 KiB, total 4 MiB
Net: eth0: mvpp2-0, eth1: mvpp2-3, eth2: mvpp2-4 [PRIME], eth3: mvpp2-5
Marvell>>
I used the GCC 7.3.0 cross toolchain (aarch64-linux-gnu-gcc, ...) from Debian testing.
Ubuntu 18.04 is at GCC 7.3.0 as well.
I haven't tried to use Debian cross toolchain. I planned to switch to GCC 7.3.0 once it get released by Linaro.
I suggest you to use the lasted available Linaro AARCH64 binary releases for your builds.
I ran into the same issue with openSUSE GCC 7.3.1: Distro toolchains are starting to default to PIE. You explicitly need to disable PIE for your target code via -fno-PIE or similar compiler options. Upstream TF-A's detection code is still incomplete though, it only works when the compiler was configured with --enable-default-pie whereas openSUSE uses a defaults file that can globally be installed and removed without reconfiguring GCC.