Problem with IRQ_N negation (deassertion) of LAN8651 device after RESET
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I'm trying to solve a following problem:
I'm using MicroE's Two-wire click ethernet. My goal is to use LAN8651 device.
The problem is with the reset. The IRQ_N pin is pulled up to 3.3V with 10kOhn resistor.
When I do issue GPIO based reset with asserting RESET_N pin, the IRQ_N goes high (as expected) and then is pulled low (as expected) after ~5.3 ms.
Moreover, when I want to use the SW based reset (OA_RESET - 0x3 register write 0x1), I can observe that IRQ_N also is asserted.
Such behaviour seems to be correct.
The problem is that IRQ_N doesn't get negated (i.e. goes high). It is all the time low.
I can access the LAN865x with SPI (read ID, etc.). After any of those resets (both GPIO and SW based) I do see:
STATUS0 => 0x40, which is expected.
Then I do write 0x40 to STATUS0 -> bit6 (RESETC) is R/W1C
After reading the same register - I do receive 0x00 (it has been cleared).
Then I write 0x8006 to OA_CONFIG0.
I would like to ask:
If above steps are enough to have the LAN8651 (version B0, silicon rev.1) properly configured and observe IRQ_N
as high (deasserted). Or do I need to do the "configuration" - like InitChip and write the TC6_MEMMAP?
To ask in other words - is the default setup (after PoR or RESET_N reset) with RESETC cleared (by writing 1) and SYNC set enough to have IRQ_N line deasserted?
Dear Mr. Majewski,
the Int-pin is not only pulled down for status changes. It is also used for Ethernet TX and RX purposes.
After the initialization is over, the rule is, whenever the Int-pin is low, we need to send out an empty data chunk. In the received MISO footer, we need to parse the EXST-Flag and the RDA, TXC values. Depending on the situation multiple actions have to be taken. Is this code getting executed at your side?
Best regards,
Thorsten Kummermehr
p.s. Please do not use the "Linux Mainline Patch Mailing List" to report microcontroller related issues and questions.
The Int-pin is not only pulled down for status changes. It is also used for Ethernet TX and RX purposes.
I would then expect that after writing the 1 to RESETC the IRQ_N line would go high at least once. When I do measure it with
mine oscilloscope, it doesn't go high at all.
This is the problem - as I do catch falling edge of IRQ_N to trigger interrupt to read data from LAN865x module.
After the initialization is over, the rule is, whenever the Int-pin is low, we need to send out an empty data chunk.
Have I understood it correctly, that after clearing RESETC (by writing 1 to OA_STATUS0), I must also send an empty data chunk to get the IRQ_N line got high?
In the received > MISO footer, we need to parse the EXST-Flag and the RDA, TXC values. Depending on the situation multiple actions have to > be taken. Is this code getting executed at your side?
No, I did not go into this step yet - I wanted to have first clear situation with IRQ_N pin, so I can add extra code.
I will read empty data chunk from LAN865x and share results.
Ok. I can confirm that to have the LAN8651 rev. B0 IRQ_N negated (i.e. deasserted) it is required to send empty chunk to it and hence read the footer.
Moreover, it may happen that STATUS0 register would be 0x0, but the IRQ_N goes low and footer indicates that there is some data ready to be read.
After the initialization is over, the rule is, whenever the Int-pin is low, we need to send out an empty data chunk.
Is this documented in OA TC6? Or this this a LAN8561 specific thing?
@lunn In the LAN8651 doc at "4.1.2 Startup Sequence" there is no explicit mention that reading an empty data chunk is required.
The aforementioned documentation only asks for clearing RESETC bit in OA_STATUS0 and set SYNC to show that the device is ready for transmitting/receiving frames.
Please be also aware that I do only have LAN8651 rev. B0 device. Maybe B1 has other behavior.
In the Linux driver patch the chunk is not read after RESETC is cleared, so the IRQ line would stay asserted (low) after completion of the interrupt. However, maybe some other thread is started (like RX one) and it performs this read? This shall be double checked IMHO.
It is cleary specified in the TC6 spec what to do in case of asserted INT-pin:
TC6-Spec-V1.1
Chapter 7.7, Page 31:
When the SPI host detects an asserted IRQn from the MAC-PHY, it should initiate a data chunk transfer to
obtain a current data footer
@tkummermehr - Thanks for the clarification - that was the missing puzzle.
It is cleary specified in the TC6 spec what to do in case of asserted INT-pin: TC6-Spec-V1.1
Thanks. That makes it clear the Linux OA TC6 core code should handle this data chunk read unconditionally. We don't need a quirk for the LAN8651.
The interesting part of implementing the Linux OA TC6 core code is understanding how different vendors got their implementation wrong, or interpreted the standard differently, and so need quirks....
@tkummermehr @lunn - Thanks for help :-)