NVlabs/timeloop

How Instances, meshX and meshY are related in the sparse_tensor_core_like example design and storage attr doubt

MustafaFayez opened this issue · 4 comments

Hi,

I am confused about the arch.yml input file of the example sparse_tensor_core_like in $HOME/timeloop-accelergy/timeloop-accelergy-exercises/workspace/baseline_designs/example_designs/sparse_tensor_core_like

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How do we have 256 PE instances and meshX & meshY are 16 & 64, respectively. I tried changing the number of PE instances and I see assertion errors. I want to understand the relation between instances, meshX and meshY. In buffer.cpp it seems instances=meshX*meshY.

Also, can you clarify the relation between n_banks and read/write bandwidth in the storage class attributes? When I specify the r/w bandwidth, is it for one bank or all banks? one instance or all instances?

Thank you.

The number of instances of a specific component needs to be interpreted hierarchically. In this architecture, there are 4 subpartitions (Subpartition[0..3]), each of which has 256 PEs, so in total, we have 1024 PEs.

n_banks and bandwidth are independent attributes, and the tool does not enforce any rules to relate the two --- we assume the user-specified attributes can be realized with design-specific implementations. The bandwidth is for one instance, and all identical instances share the same bandwidth.

Thank you, Nellie. Also, is n_banks related to width and depth of a memory instance as in the total width used in the tool equals n_banks * width attrs? and is n_banks for one instance or all instances?

After looking at the Accelergy cacti wrapper code, I think SRAM width and depth are for all banks and not for one bank only. is that right?

Yes, the width and depth are for the overall capacity, and the number of banks attribute will tell the plug-in to instantiate multiple banks.