Naseefabu

Naseefabu's Stars

• cpp-best-practices/cmake_template

  CMake for C++ Best Practices

  Language:CMake1.2k122

• mit-pdos/xv6-riscv-book

  Text describing xv6 on RISC-V

  Language:TeX671143

• axboe/liburing

  Library providing helpers for the Linux kernel io_uring support

  Language:C2.9k406

• ddeka0/AsyncIO

  A CPP wrapper for asynchronous socket server using linux's latest IO_URING API

  Language:C++252

• xuanyi-fu/xynet

  network library based on io_uring and C++20 coroutine

  Language:C++10114

• wg/wrk

  Modern HTTP benchmarking tool

  Language:C38.1k3k

• yasukata/tinyhttpd-lwip-dpdk

  A tiny HTTP server built on lwIP and DPDK

  Language:C348

• SungHoHong2/DPDK-Experiment

  Collection of DPDK Experiments

  Language:Makefile113

• airbus-seclab/c-compiler-security

  Security-related flags and options for C compilers

  Language:Python18516

• real-logic/aeron

  Efficient reliable UDP unicast, UDP multicast, and IPC message transport

  Language:Java7.4k894

• asatarin/testing-distributed-systems

  Curated list of resources on testing distributed systems

  Language:HTML2.5k225

• KDE/heaptrack

  A heap memory profiler for Linux

  Language:C++3.4k203

• OpenHFT/Chronicle-Queue

  Micro second messaging that stores everything to disk

  Language:Java3.3k535

• muditbhargava66/High-Frequency-Trading-FPGA-System

  The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, order matching engine, custom IP core, and risk management module for accelerated and reliable trade execution.

  Language:Verilog629

• tigerbeetle/tigerbeetle

  The financial transactions database designed for mission critical safety and performance.

  Language:Zig10.7k520

• nperrem/mserve

  Enhanced mserve load balanced solution

  Language:Batchfile103

• ninja-quant/ninjabook

  A lightweight and high-performance order-book designed to process level 2 and trades data. Available in Rust and Python

  Language:Rust15917

• openhwgroup/cvw

  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

  Language:SystemVerilog272198

• aliireza/packetmill

  PacketMill: Toward per-core 100-Gbps Networking

  Language:Gnuplot629

• shuveb/loti-examples

  Source code for example programs from Lord of the io_uring guide

  Language:C15532

• ronniec95/black_scholes

  A SIMD based black scholes pricer using the http://crates.io/wide crate

  Language:Rust647

• pabloariasal/couring

  C++20 Coroutines and io_uring

  Language:C++473

• shuveb/io_uring-by-example

  A companion repository for the io_uring by Example article series

  Language:C37656

• sadhbh-c0d3/lock-free

  Low Latency Ring-Buffer | Atomic Smart Pointer | Lock & Wait Free Utilities

  Language:C509

• gilescope/atoi_radix10

  Rust port of https://kholdstare.github.io/technical/2020/05/26/faster-integer-parsing.html

  Language:Rust212

• vgatherps/simd_decimal

  vectorized decimal parsing

  Language:Rust11

• Tredzone/simplx

  C++ development framework for building reliable cache-friendly distributed and concurrent multicore software

  Language:C++6519

• cpp-best-practices/gui_starter_template

  A template CMake project to get you started with C++ and tooling

  Language:CMake2.5k446

• ZipCPU/wbuart32

  A simple, basic, formally verified UART controller

  Language:Verilog28348

• aolofsson/awesome-opensource-hardware

  List of awesome open source hardware tools, generators, and reusable designs

  Language:Python1.9k177