Phzera
BSc. Telecommunications Engineer (UNICAMP) / FPGA Design Engineer / Hobbyist
@Pi-Tecnologia (https://www.pitec.co/)Campinas/SP, Brazil
Phzera's Stars
seldridge/verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
verilator/example-systemverilog
verilator/uvm
Universal Verification Methodology (UVM) base libraries, with edits for Verilator
VUnit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
pConst/basic_verilog
Must-have verilog systemverilog modules