Support for SystemVerilog Interfaces

[kiteloopdesign]

I think veriloggen does not support SV interfaces at the moment?

Are these on the pipeline? It should not be too much of an update to add suport for them given the syntax and structure is pretty similar to an usual verilog module

Thanks

[shtaxxx]

SystemVerilog support by Pyverilog is in-progress. After that, Veriloggen also supports SystemVerilog.

[kiteloopdesign]

Awesome, looking forward to it
Thanks Shinya-San