RRZE-HPC/likwid

Haswell MEM formulas not consistent with the metrics

Closed this issue · 1 comments

SHORT L3 cache bandwidth in MBytes/s
EVENTSET
FIXC0 INSTR_RETIRED_ANY
FIXC1 CPU_CLK_UNHALTED_CORE
FIXC2 CPU_CLK_UNHALTED_REF
MBOX0C1 DRAM_READS
MBOX0C2 DRAM_WRITES
METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
CPI FIXC1/FIXC0
Memory load bandwidth [MBytes/s] 1.0E-06*MBOX0C1*64.0/time
Memory load data volume [GBytes] 1.0E-09*MBOX0C1*64.0
Memory evict bandwidth [MBytes/s] 1.0E-06*MBOX0C2*64.0/time
Memory evict data volume [GBytes] 1.0E-09*MBOX0C2*64.0
Memory bandwidth [MBytes/s] 1.0E-06*(MBOX0C1+MBOX0C2)*64.0/time
Memory data volume [GBytes] 1.0E-09*(MBOX0C1+MBOX0C2)*64.0
LONG
Formulas:
L3 load bandwidth [MBytes/s] = 1.0E-06*L2_LINES_IN_ALL*64.0/time
L3 load data volume [GBytes] = 1.0E-09*L2_LINES_IN_ALL*64.0
L3 evict bandwidth [MBytes/s] = 1.0E-06*L2_TRANS_L2_WB*64.0/time
L3 evict data volume [GBytes] = 1.0E-09*L2_TRANS_L2_WB*64.0
L3 bandwidth [MBytes/s] = 1.0E-06*(L2_LINES_IN_ALL+L2_TRANS_L2_WB)*64/time
L3 data volume [GBytes] = 1.0E-09*(L2_LINES_IN_ALL+L2_TRANS_L2_WB)*64

Thanks for reporting. The inconsistency got fixed in e64aae0