Version 2.00 Phase/buffer instability for on-trigger acquisition

[werefkin]

Hi, I am testing the new version and found out that if the on-trigger acquisition is running in a loop, often the buffer gets filled with mistakes.
To check I generate a 20 Hz asymmetric Ramp signal (and Sync signal for triggering) with an external source, and repeat the acquisition 20 times. The average elapsed time per single event is 656 ms, which is shorter than the time scale of the buffer.
The recorded signals look like that:

and for a single waveform:

The same can be observed with other decimation factors, a quick fix to it is to introduce a trigger delay of half of the buffer size: i.e. rp_s.tx_txt('ACQ:TRIG:DLY 8192')

then the measurements are coherent, and elapsed time (average) is 1.19s which is a bit longer than the time scale of the buffer (at this decimation):

[b-swat]

It's not a problem. It really does work.
Once upon a time, developers made a function to fill the buffer, and by default the buffer is filled only by half. To fill the entire buffer, you need to specify a trigger delay of half the buffer)).
Otherwise, in the first half there will always be data that is not valid.

This function was made for the oscilloscope when the default trigger is set to half of the buffer.

The correct algorithm for working with the buffer then looks like this:

• Start ADC
• Wait half the time of the buffer (it is necessary that the data be written before the trigger)
• Turn on the fpga trigger and start recording data.

I have long had a desire to change this function, but people have already written scripts for such logic.