questions about cryopipeline

[shlin21]

Hello, I am interested in your research of cryomodel, and would like to learn about your code. But when running the cryopipeline, I encountered some issues, could you please give me any suggestions about them？

1. The power results reported after running cryopipeline/logic_model.py show the global operating voltage = 1.1V, while the nom_voltage in freepdk_45nm/stdview/stdcell.lib is 1.1V as well. But the voltage of reference_pgen in logic_model.py is 1.25V. In logic_model.py-line 225-227, it seems that the data of reference_pgen and target_pgen is used to offset the differences in voltage and other parameters between the stdcells of lib and target design. Could you please give me any advice on how to comprehend the data processing of design power in logic_model.py-line 225-227 and the different voltages?

2. In logic_model.py-line 218-219, the static power reduction is calculated by dividing the sum of Isub and Igate. May I ask why the voltage isn’t taken into consideration here, for example, (V*(Isub+Igate))target/(V*(Isub+Igate))ref?

[dongmoon-min]

Hello, shlin21.
Thanks for your interest in our model.

First of all, we use 1.25V because it is the peak operating voltage of 45nm Intel CPU under turbo boost mode.
As we compare 45nm Intel CPU with our architecture in our paper, we set the voltage to 1.25V.
Please set the baseline voltage at 185 to the voltage that you want (e.g., 1.1V following freePDK, 1.0V following PTM).
Note that Vth0 value (0.46893V) is based on PTM which follows the ITRS roadmap.

Meanwhile, for the static power reduction, your suggestion is really valid.
I think we omitted them while cleaning up the code before the tool release.
I will fix the line 218-219 as you mentioned.

[shlin21]

Hello, thank you for your reply so much, it really helps me.
I’m glad my question is valid.

But I encountered another issue. In logic_model.py-line 225-227, I find the code uses transistor data to calculate target power under 77K only. Since the voltage in 45nm FreePDK is 1.1V, I wonder whether the reference power under 300K should also be calculated like 77K(line 225-227), if I use different reference voltage (e.g.,1.3V, 1.5V) from the FreePDK, and, whether the variable power_total[0] is the power of target design working in the condition of 300K, using transistor of pgen_300K(line 185)?
Could you please give me any suggestions about them?

Thank you!

[dongmoon-min]

We appreciate your kindness for sharing the issue.

I added the new code to compensate for the different operating voltage at 300K.
I think the new code does not much affect the relative numbers (i.e., speedup, power reduction) used in our paper, but it will change the absolute numbers (e.g., critical-path delay, power).

Please check our update and contact us if any problem still exists.
Thank you again :)

[shlin21]

Thanks for your response, it's my pleasure to share the issue.
I rerun the cryopipeline with updated logic_model.py, and everything looks fine.
Thank you very much!