Change power stack status lines to be driven by I2C GPIO expander devices

[npetersen2]

This is a question issue and a proposal for potential changes on future hardware revisions:

Background

All the power stack status lines (four per port, 32 total lines) are directly connected to the FPGA through level shifters. They are grouped as four banks: A ... D. Each power stack has one of each A..D. Since all status signals must go through level shifters, the direction must be selected for the whole bank.

The present design has a couple major flaws:

• All power stacks must use the same direction status lines, since the A...D direction is set per group, not per power stack.
• The status lines consume 32 digital lines on the FPGA for nominally constant valued signals -- the design is basically out of FPGA I/O, so this limits future designs updates.

Note that some expansion boards (like the DAC) have been designed to actually communicate with the AMDC using the power stack status lines! This was not the desired function; the GPIO ports should be used for external boards.

Furthermore, the status lines have not been used for any high-bandwidth content as of yet... they are supposed to be used for indicating faults, resets, ready signals etc. These are generally low-frequency. Note that the latency between a fault indication and firmware intervention is critical -- this is the one good aspect of having the status lines directly connected to the FPGA.

Proposal

I propose we change all status lines to be driven and interfaced using GPIO expander ICs which communicate over I2C and have external interrupt support. For example, this device is about $1 and can drive eight status lines, both input and outputs.

This would GREATLY simplify the status line interface design by helping layout, reducing BOM, and adding more customizable input/output settings. Also, by using the interrupt support on the IC, low-latency firmware action is still possible in response to faults.

The only negative of this idea is that the bandwidth of the status lines would most likely be reduced to well under ~50kHz since I2C is limited to 400kHz clock. This is perfectly fine for actual status lines, but would hinder support for external boards. As the intended function of the status lines is for status information, I think this is fine.