SheaCai's Stars
CyC2018/CS-Notes
:books: 技术面试必备基础知识、Leetcode、计算机操作系统、计算机网络、系统设计
youngyangyang04/leetcode-master
《代码随想录》LeetCode 刷题攻略:200道经典题目刷题顺序,共60w字的详细图解,视频难点剖析,50余张思维导图,支持C++,Java,Python,Go,JavaScript等多语言版本,从此算法学习不再迷茫!🔥🔥 来看看,你会发现相见恨晚!🚀
NVIDIA/FasterTransformer
Transformer related optimization, including BERT, GPT
Lyken17/pytorch-OpCounter
Count the MACs / FLOPs of your PyTorch model.
OAID/Tengine
Tengine is a lite, high performance, modular inference engine for embedded device
sksq96/pytorch-summary
Model summary in PyTorch similar to `model.summary()` in Keras
openmlsys/openmlsys-zh
《Machine Learning Systems: Design and Implementation》- Chinese Version
microsoft/AI-System
System for AI Education Resource.
jcjohnson/cnn-benchmarks
Benchmarks for popular CNN models
drh/lcc
The lcc retargetable ANSI C compiler
Xilinx/Vitis-AI
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
intel/llvm
Intel staging area for llvm.org contribution. Home for Intel LLVM-based projects.
google/xls
XLS: Accelerated HW Synthesis
microsoft/nnfusion
A flexible and efficient deep neural network (DNN) compiler that generates high-performance executable from a DNN model description.
nebuly-ai/nos
Module to Automatically maximize the utilization of GPU resources in a Kubernetes cluster through real-time dynamic partitioning and elastic quotas - Effortless optimization at its finest!
chipsalliance/chisel-template
A template project for beginning new Chisel work
BRTResearch/AIChip_Paper_List
calyxir/calyx
Intermediate Language (IL) for Hardware Accelerator Generators
geniayuan/datasciencecoursera
for Data Science class on Coursera
IBM/AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
eth-cscs/COSMA
Distributed Communication-Optimal Matrix-Matrix Multiplication Algorithm
abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
mangpo/greenthumb
StanfordAHA/Halide-to-Hardware
ucb-bar/cosa
A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
GATECH-EIC/AutoDNNchip
pku-liang/TensorLib
A Spatial Accelerator Generation Framework for Tensor Algebra.
StanfordVLSI/Genesis2
A home for Genesis2 sources.
SheaCai/optimus
This is the implementation of the paper [Optimus: Towards Optimal Layer-Fusion on Deep Learning Processors].
Jagadeepram/linear-equation-solver-DE1-SoC
Accelerate Linear Equation System Solver on DE1-SoC development Board