Clock domain crossing issues in m26_rx

[laborleben]

Reading the timestamp uses a clock from an external source where the timestamp itself is synchronous to an internal clock.

See:

basil/firmware/modules/m26_rx/m26_rx_core.v

Line 149 in 07b7cf3

reg [31:0] TIMESTAMP_save;

[themperek]

The user has to know what is dong and use CLK_RX to generate the timestamp (or any other clock in proper time domain).

Actually issue is in pymosa here: https://github.com/SiLab-Bonn/pymosa/blob/master/firmware/src/mmc3_m26_eth.v#L558-L570
And it is done correctly (as far as I can see).

[laborleben]

Yes, with the gray coded timestamp there are no CDC issues. I wasn't aware of the fact.