TerosTechnology/vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
VHDLGPL-3.0
Issues
- 1
- 0
Auto documentation bugs/wrong documentation for VHDL
#704 opened by ArnePret - 0
RivieraPro search is incorrect
#703 opened by ArnePret - 2
- 0
- 2
Recommended flow for standalone CLI documenter?
#685 opened by davidgussler - 1
- 1
[Question] Syntax Checking while Typing
#692 opened by thomas-woehrle - 4
- 13
[Question] How to use testbenches?
#699 opened by thomas-woehrle - 1
- 0
Verify Setup issue
#697 opened by victobui - 0
@keepports doesnt work
#695 opened by monkey265 - 1
- 4
Python Virtual Environments not Usable
#691 opened by thomas-woehrle - 1
Add files button does nothing
#690 opened by jakefreeman - 6
- 0
- 0
Snippet suggestions appear twice when using TerosHDL with VHDL-LS extension
#683 opened by davidgussler - 3
Indentation following vhdl 'when' clause
#678 opened by SittingDuc - 0
Why my code doesn't produce a FSM ?
#682 opened by FinnNGrace - 3
Quartus path resolution incorrect for windows, SILENT fallback to QUARTUS_ROOTDIR
#671 opened by dbee-novosound - 0
Issues in the configuration
#680 opened by ecstrema - 3
Quartus crashes when compiling
#679 opened by ecstrema - 33
Update/Upload TerosHDL on OpenVSX
#654 opened by gfcwfzkm - 0
Failed to access library 'C:\Users\namhe\.teroshdl_fryIl_' at "C:\Users\namhe\.teroshdl_fryIl_".TerosHDL: modelsim(vlog-19)
#677 opened by FinnNGrace - 2
Spaces in Project Name Broken?
#668 opened by jchang-endiag - 1
Add all HDL files from a directory and subdirectories doesn't do anything
#666 opened by JennySmith888 - 1
VHDL Standalone Formatter Indentation prints the value its set to (e.g 4) when formatting the document
#676 opened by finc00 - 1
Formatter s3sv not working
#670 opened by IMucaMI - 5
- 7
Downgrades from v6.0.1 to v6.0.3
#661 opened by ArnePret - 2
- 3
Q: TerosHDL and Python virtual environments
#660 opened by mkaiser - 0
Error when trying to instantiate an entity containing a generic type (VHDL 2008)
#658 opened by vdahle - 0
VHDL comment type for Verilog testbench template
#656 opened by SebekO - 0
- 1
- 0
- 4
- 1
Unable to select NVC as simulator
#651 opened by gfcwfzkm - 1
VHDL LS can't find ieee.numeric_std.all because of Copyright symbol in string
#646 opened by ArnePret - 1
- 1
- 1
verilog snippets error
#632 opened by narutozxp - 1
TerosHDL Evaluate don't work well in V6.0.1
#634 opened by narutozxp - 5
Support for specific VUnit project
#641 opened by james-ziegler - 1
Add **Chinese** language support
#643 opened by miilTgy - 0
- 0