VLSIJEXA
Hi, I am from VLSI JEXA Technology and I am learning HDL, Low-Power VLSI Design and Verification. I like to learn German and Russian .
@mnitJaipur
Pinned Repositories
Basic-Verilog
This repository showcases a collection of basic Verilog projects developed using Vivado . The projects focus on fundamental concepts in digital logic, including combinational logic (e.g., adders, multiplexers), sequential logic (e.g., flip-flops, counters), and simple state machines.
FIFO-singleclock-design
memories-designing
ALU-Power-Optimization-via-Clock-Gating-and-CLA
My-Verilog
RTL-Projects
Mini Project
High-Speed-and-Low-Power-carry-select-adder-with-BEC
ALU-Design
4-Bit ALU Design
Automatic-Washing-Machine-Controller
barrel-shifter
This is a simplified representation of how a barrel shifter operates. The actual implementation would require designing the shift logic (using multiplexers or combinatorial logic) based on the number of bits to shift and the direction.
VLSIJEXA's Repositories
VLSIJEXA/new-project
VLSIJEXA/Basic-Verilog
This repository showcases a collection of basic Verilog projects developed using Vivado . The projects focus on fundamental concepts in digital logic, including combinational logic (e.g., adders, multiplexers), sequential logic (e.g., flip-flops, counters), and simple state machines.
VLSIJEXA/Piezoelectric-Energy-Generator
The aim is to design and simulate a MEMS-based system that integrates piezoelectric materials to convert mechanical stress into electrical energy or signals, possibly for energy harvesting or sensing applications.
VLSIJEXA/FSM_lock
Need to design an FSM-based lock in Verilog. The lock opens with sequences like aabbba, aba, aaaaba, or a0bb0a.aabaa,aabbbbaa 'a' and 'b' can repeat, but after 'b', 'a' appears once to open the lock. '0' means stay in the same state
VLSIJEXA/RISC-V
RISC-V Single-Cycle Processor using Verilog
VLSIJEXA/High-Speed-and-Low-Power-carry-select-adder-with-BEC
VLSIJEXA/invertor_LTspice
VLSIJEXA/COMSOL-version5.2a
Multiphysics simulation
VLSIJEXA/portfolio
VLSIJEXA/UVM
VLSIJEXA/System-Verilog
learning system verilog
VLSIJEXA/VLSIJEXA
My personal repository
VLSIJEXA/TCL
VLSIJEXA/C
VLSIJEXA/ALU-Power-Optimization-via-Clock-Gating-and-CLA
VLSIJEXA/FIFO-singleclock-design
VLSIJEXA/RTL-Projects
Mini Project
VLSIJEXA/My-Verilog
VLSIJEXA/Low-Power-VLSI-Design-Circuit
VLSIJEXA/Automatic-Washing-Machine-Controller
VLSIJEXA/vending-machine
VLSIJEXA/personal_note
VLSIJEXA/ALU-Design
4-Bit ALU Design
VLSIJEXA/basic-VHDL
VHDL Implementations:logic Gates, Flip-Flops, Adders, Mux, and Encoders/Decoder This repository contains VHDL implementations of essential digital circuits used in FPGA and ASIC design .This repository is useful for digital design projects and for understanding different VHDL modeling styles: behavioral, structural, and dataflow.
VLSIJEXA/Reconfigurable-ALU-with-Dynamic-Power-Management
VLSIJEXA/memories-designing
VLSIJEXA/barrel-shifter
This is a simplified representation of how a barrel shifter operates. The actual implementation would require designing the shift logic (using multiplexers or combinatorial logic) based on the number of bits to shift and the direction.