VVViy's Stars
chipsalliance/Cores-VeeR-EH2
pulp-platform/pulpino
An open-source microcontroller system based on RISC-V
mntmn/amiga2000-gfxcard
MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog
lowRISC/opentitan
OpenTitan: Open source silicon root of trust
analogdevicesinc/hdl
HDL libraries and projects
pConst/basic_verilog
Must-have verilog systemverilog modules
KastnerRG/riffa
The RIFFA development repository
open-sdr/openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
tensor-compiler/taco
The Tensor Algebra Compiler (taco) computes sparse tensor expressions on CPUs and GPUs
NervanaSystems/ngraph
nGraph has moved to OpenVINO
plaidml/plaidml
PlaidML is a framework for making deep learning work everywhere.
ONNC/onnc
Open Neural Network Compiler
pytorch/glow
Compiler for Neural Network hardware accelerators
llvm/llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
prakhar1989/awesome-courses
:books: List of awesome university courses for learning Computer Science!
basicmi/AI-Chip
A list of ICs and IPs for AI, Machine Learning and Deep Learning.
OpenAtomFoundation/TobudOS
开放原子开源基金会孵化的物联网操作系统,捐赠前为腾讯物联网终端操作系统TencentOS Tiny
BiscuitOS/BiscuitOS
Common scripts to build BiscuitOS
terryum/awesome-deep-learning-papers
The most cited deep learning papers
ChristosChristofidis/awesome-deep-learning
A curated list of awesome Deep Learning tutorials, projects and communities.
floodsung/Deep-Learning-Papers-Reading-Roadmap
Deep Learning papers reading roadmap for anyone who are eager to learn this amazing tech!
jackfrued/Python-100-Days
Python - 100天从新手到大师
TheAlgorithms/Python
All Algorithms implemented in Python
NationalSecurityAgency/ghidra
Ghidra is a software reverse engineering (SRE) framework
embedeep/Free-TPU
Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classification, detection, and segmentation problem.
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
bluespec/Flute
RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
westerndigitalcorporation/swerv_eh1
A directory of Western Digital’s RISC-V SweRV Cores
chipsalliance/riscv-dv
Random instruction generator for RISC-V processor verification
pulp-platform/pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.