VeriSilicon/TIM-VX

Default layout inference pass

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Hi, I get these warnings when running an int8 quantized model on I.MX 8M Plus using the vx delegate:

W [HandleLayoutInfer:332]Op 162: default layout inference pass.
W [HandleLayoutInfer:332]Op 56: default layout inference pass.

What does the warnings mean?

The model performs worse on NPU than CPU which I'm guessing might be related to these warning