/MS125-RISC-V-simulator

A sequential and pipelined CPU simulator over the RISC-V ISA. Part of Principle and Practice of Computer Algorithms project.

Primary LanguageC++MIT LicenseMIT

RISC-V-simulator

This is the RISC-V Simulator implementation homework of MS125: Principle and Practice of Computer Algorithms.

Requirements: PPCA_2020: RISC-V simulator. Please refer to documentation for details.

Other documentations are files for reference, the repository owner claims no right to these files. Use them at your own risk.

To build binary executables, run commands:

Implementation commands
Sequential make code_seq
Pipeline make code_pip
Pipeline with prediction make or make code

and execute with ./code.

Testcases are located in dataset. The plain files comes from Repo. riscv-testcases and files in subdirectories are created under this project.

See detailed description in structures.md.