WICG/serial

Clarify behavior of hardware flow control

reillyeon opened this issue · 0 comments

The hardware flow control mode should be documented more completely. In the Chromium implementation it means that RTS/CTS-based flow control is used, where RTS is set high when there is available receive buffer space and set low when the receive buffer is dangerously full. Similarly, the CTS signal is monitored and data only sent when CTS is high.