Invalid record Error - Vitis HLS Custom Input

[RicDen]

Hello,

I am trying to pass llvm bc files to the Vitis front end, but I get an "error: Invalid record".
The only kind of .bc codes I got to work is the LLVM_CUSTOM_OUTPUT file, which set as LLVM_CUSTOM_INPUT file.
However, even if I only use llvm-dis-7 and and then llvm-as-7 to just convert it to LLVM IR and back to .bc formata, the input is not anymore accepted and I get the invalid record error.

As I can't find any documentation regarding this and the error log does not give me more than this one line, I suppose it is a bug or it's something I can't find.

I reduced everything and I am just using the cpp code from the custom llvm example from this repository.
Below you can see my TCL script.

# Open a project and remove any existing data
open_project -reset proj

# Add kernel and testbench
add_files hls_example.cpp
add_files -tb hls_example.cpp

# Tell the top
set_top example

# Open a solution and remove any existing data
open_solution -reset solution1

# Set the target device
set_part "virtex7"

# Create a virtual clock for the current solution
create_clock -period "300MHz"

### The following variables must be set before csynth_design

#set ::LLVM_CUSTOM_OPT [pwd]/../../llvm/hls-build/bin/opt
set ::LLVM_CUSTOM_INPUT [pwd]/test_out1.bc
#set ::LLVM_CUSTOM_OUTPUT [pwd]/test_out1.bc

# This example assumes that the local opt binary has some customized behavior (no custom passes called here)
# Do not use global namespace (::) for variables used in LVM_CUSTOM_CMD
set ::LLVM_CUSTOM_CMD {$LLVM_CUSTOM_OPT $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT}

# Compile and runs pre-synthesis C simulation using the provided C test bench
#csim_design

# Synthesize to RTL
csynth_design

# Execute post-synthesis co-simulation of the synthesized RTL with the original C/C++-based test bench
#cosim_design

I am running Vitis 2020.2 on Ubuntu 18.04.
I also tried to work with llvm 9 or other, but the issue remains and I think it should work with llvm 7.

I woulld appreciate any help a lot. Thank you very much!

[keryell]

The problem is that this is not supported and it is not clear what is the exact version of the Clang/LLVM used in Vitis.
You might look at https://github.com/triSYCL/sycl/tree/sycl/unified%2Fnext to find some experiment about how to feed Vitis with some LLVM IR.