Xilinx/Vitis-HLS-Introductory-Examples

Examples in Data_driven don't work. I get a error when running the run_hls.tcl

Malarius1999 opened this issue · 1 comments

 #include "hls_task.h"
                      ^
compilation terminated.
make: *** [obj/test_tb.o] Error 1
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 1 seconds. CPU system time: 0 seconds. Elapsed time: 0.785 seconds; current allocated memory: 288.356 MB.
4
    while executing
"source run_hls.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 [list source $arg] "

INFO: [Common 17-206] Exiting vitis_hls at Mon Nov 14 15:25:44 2022...

My fault. I wasn't on the newest version