[ERROR] Issue with Bit Width Exceeding Limit in HLS Stream as Intermediate Variable

[hanghug]

Hello,

I am encountering an issue while using hls::stream as an intermediate variable in my project. The compiler is indicating that the bit width is too large, exceeding the 4096 limit. Here's the context of my problem:

I created my own data structure, similar to hls::vector. Below is the relevant code snippet:

#ifdef __SYNTHESIS__
#define SYN_PRAGMA(PRAG) _Pragma(#PRAG)
#else
#define SYN_PRAGMA(PRAG)
#endif

template <typename T, unsigned N>
struct array {
    typedef T value_type;
    static const unsigned size = N;

    T data[N];

protected:
  INLINE void pragma() const {
    SYN_PRAGMA(HLS DISAGGREGATE variable=this)
  }

public:
    INLINE array() {
       pragma();
       SYN_PRAGMA(HLS ARRAY_PARTITION variable=this->data complete)
    }

    // ... [Additional member functions]
};

Then, I declared a data type as follows:

typedef array<ap_fixed<32,8>, 512> input_t;
hls::stream<input_t> data_recv;
#pragma HLS STREAM variable=data_recv

However, when I declare a data stream wrapped with the input_t type inside a function, I encounter the aforementioned error, From the log file, I noticed the message:
"INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'data_recv' with compact=bit mode."It seems to perform an Aggregate operation.
Is there a way to perform Disaggregate? I have not encountered this error when using Vivado HLS previously.