Xilinx/Vitis-HLS-Introductory-Examples

What is the expected result of example "Dataflow/Bypassing/input_bypass" ?

aniltirli opened this issue · 2 comments

I don't see any performance degradation in terms of latency and II when compared the synthesis reports of problem and solution. What do you mean by "performance degradation" stated in ReadMe?

Hi @aniltirli, are you comparing the synthesis reports or cosimulation reports? To observe the dataflow performance, you will need to review the cosimulation report as the synthesis report will not show the effects of the dataflow optimization.

Marking this closed.