10MHZ clock might be too fast for the FLASH chip I specified.
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While my board has been running fine at 10MHZ, the timing on FLASH_MREQ is too tight to meet the official worst-case specification... even with the 55ns version of the FLASH.
The solution if you run into trouble is to run the main clock at 8MHZ. I will change the design to officially run at 8.
On the YouTube comments: https://www.youtube.com/watch?v=w5LYCHml4A8
Torshak observed:
As always, great and very helpfull video.
I have a observation regarding memory access time though. I am trying to read Z80 opcode fetch timings, and I don't think you have entire 150ns. Yes, you have 1.5 periods, but... MREQ signal does not fall together with clock falling egde but it takes it up to 55 ns. Then Z80 expects data to be stable 25 ns before rising edge of the clock. (all timings for 10Mhz version) so you are left with 70ns, and that's wihtout glue logic. Of course this is almost the absolute worst scenario. Unless I am reading it wrong... which would not be the first time ;)
Then I replied with this:
BLAST IT ALL!!!! I was looking at a page of the datasheet that included a wait-state in the diagram! It looks like the 55 and 25 numbers are right for the 10MHZ Z80.. The FLASH that I used has a 70ns access time (and the RAM is 55). Revising my understanding and NOT including a stinking wait-state the tightest memory cycle duration is 150ns - 55ns - 25ns = 70ns.
Fortunately, the SRAM has no decoding per-se and the OE to DATA time is 30ns (which is fine with the extra U10 27ns delay.)
The FLASH is a bit more of a problem. FLASH_MREQ can be delayed by U10 by up to 27ns.
I hang my head in shame!
Luckily, at 8MHZ, we see 125*1.5 - 60 - 30 = 97.5nsec
The worst-case FLASH_MREQ time (delayed by 27ns) is then 70.5nsec :-D
I think I will /officially/ slow the main clk to 8MHZ and observe that I have been living on the edge by overclocking mine at 10!
Running at 8MHZ is within the specs and empirical evidence shows that 10MHZ is OK as well.