a4lg

binutils-gdb

cjkv-radical-index

fast-ssdeep-clus

Parallel ssdeep clustering kit

fast-tlsh

Fast TLSH-compatible Fuzzy Hashing Library in pure Rust

ffuzzy

Library to generate / parse / compare ssdeep Context Triggered Piecewise Hashes (CTPH)

ffuzzypp

C++ implementation of ssdeep-compatible fast fuzzy hashing

libffuzzy

Fast ssdeep comparison library

riscv-baremetal-playground

RISC-V Baremetal Playground

a4lg/fast-tlsh

Fast TLSH-compatible Fuzzy Hashing Library in pure Rust

a4lg/ffuzzy

Library to generate / parse / compare ssdeep Context Triggered Piecewise Hashes (CTPH)

a4lg/binutils-gdb

a4lg/collect_slice

Collect an iterator into a slice.

a4lg/docs-spec-template

a4lg/gcc

a4lg/ImHex

🔍 A Hex Editor for Reverse Engineers, Programmers and people who value their retinas when working at 3 AM.

a4lg/nugine-simd

SIMD-accelerated operations

a4lg/riscv-binutils-devmemo

binutils development memo (for RISC-V)

a4lg/riscv-c-api-doc

Documentation of the RISC-V C API

a4lg/riscv-cfi

This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.

a4lg/riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.

a4lg/riscv-crypto

RISC-V cryptography extensions standardisation work.

a4lg/riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

a4lg/riscv-indirect-csr-access

Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.

a4lg/riscv-isa-manual

RISC-V Instruction Set Manual

a4lg/riscv-isa-sim

Spike, a RISC-V ISA Simulator

a4lg/riscv-opcodes

RISC-V Opcodes

a4lg/riscv-profiles

RISC-V Architecture Profiles

a4lg/riscv-rvm-csi

RVM-CSI (RISC-V eMbedded - Common Software Interface) aims to provide a source-level portability layer providing a simplified transition path between different microcontrollers based on RISC-V. This repo contains the specification documentation, and language-specific source files for implementing the API (initially, C header files).

a4lg/riscv-sbi-doc

Documentation for the RISC-V Supervisor Binary Interface

a4lg/riscv-smcdeleg-ssccfg

Supervisor Counter Delegation Architecture Extension

a4lg/riscv-smcntrpmf

Cycle & Instret Privilege Mode Filtering Architecture Extension

a4lg/riscv-smmtt

This specification will define the Smmtt privilege ISA extensions required to support the supervisor domain isolation for many isolation use cases e.g. confidential-computing, fault isolation and so on.

a4lg/riscv-zabha

The Zabha extension provides support for byte and halfword atomic memory operations.

a4lg/riscv-zacas

riscv-zacas created from docs-spec-template template

a4lg/terminal

The new Windows Terminal and the original Windows console host, all in the same place!

a4lg/tg-nexus-trace

RISC-V Nexus Trace TG documentation and reference code

a4lg/tlsh

a4lg/translated-content

The source repository of all translated content for MDN Web Docs