Pinned Repositories
2D-Coordinate-Rotation-and-Vectoring-based-Design-Methodology-CORDIC-using-Verilog-HDL
-Device-Characterization-Lab
Advanced-Physical-Design-using-OpenLane-SKY130
This repository contains the whole summary of hands on done by Abhinav Prakash (IS22MTECH14002) during the workshop "Advanced-Physical-Design-using-OpenLane-SKY130" organised by VSD. The full RTL to GDSII flow was implemented for PICORV32A- a RISC-V based CPU core.
FPGA---Fabric-Design-and-Architecture
fpga_workshop_collaterals
Input files and commands needed for the workshop, sorted daywise
Protocols-
This repository contains the whole summary of hands on done by Abhinav Prakash (IS22MTECH14002) on the following Protocols
RISC-V-based-MYTH
This repository contains the whole summary of hands on done by Abhinav Prakash (IS22MTECH14002) during the workshop RISC-V based MYTH and understanding the architecture of RISC-V
RISC-V-CTB-Hackathon
SIGN-OFF-TIMING-ANALYSIS
This repository contains the whole summary of hands on done by Abhinav Prakash (IS22MTECH14002) during the workshop Advanced-Physical-Design-using-OpenLane-SKY130 organised by VSD. The full RTL to GDSII flow was implemented for picorv32a design a RISC-V based CPU core using OpenLANE with SKY130nm PDK.
tt06-verilog-template
Submission template for Tiny Tapeout 6 - Verilog HDL Projects
abhinavprakash199's Repositories
abhinavprakash199/Protocols-
This repository contains the whole summary of hands on done by Abhinav Prakash (IS22MTECH14002) on the following Protocols
abhinavprakash199/RISC-V-based-MYTH
This repository contains the whole summary of hands on done by Abhinav Prakash (IS22MTECH14002) during the workshop RISC-V based MYTH and understanding the architecture of RISC-V
abhinavprakash199/Advanced-Physical-Design-using-OpenLane-SKY130
This repository contains the whole summary of hands on done by Abhinav Prakash (IS22MTECH14002) during the workshop "Advanced-Physical-Design-using-OpenLane-SKY130" organised by VSD. The full RTL to GDSII flow was implemented for PICORV32A- a RISC-V based CPU core.
abhinavprakash199/RISC-V-CTB-Hackathon
abhinavprakash199/2D-Coordinate-Rotation-and-Vectoring-based-Design-Methodology-CORDIC-using-Verilog-HDL
abhinavprakash199/-Device-Characterization-Lab
abhinavprakash199/FPGA---Fabric-Design-and-Architecture
abhinavprakash199/SIGN-OFF-TIMING-ANALYSIS
This repository contains the whole summary of hands on done by Abhinav Prakash (IS22MTECH14002) during the workshop Advanced-Physical-Design-using-OpenLane-SKY130 organised by VSD. The full RTL to GDSII flow was implemented for picorv32a design a RISC-V based CPU core using OpenLANE with SKY130nm PDK.
abhinavprakash199/fpga_workshop_collaterals
Input files and commands needed for the workshop, sorted daywise