All *PROT signals are missing

[kirill-bessonov]

cocotb==1.6.2
cocotbext-axi==0.1.16
Questa Sim-64 Version 10.7f

Hello,

I am instantiate AxiLiteMaster like this:
axi_drv = AxiLiteMaster(AxiLiteBus.from_entity(dut.axi4_lite_if_inst), dut.i_clk, dut.i_rst_n)
There is an SystemVerilog's interface instance in Top module that contains all of the signals. All signals except aforementioned ones are found and basic READ/WRITE operations are working. What can causing this problem?
Also I noticed that if I do not specify cocotbext-axi's version for simulation it downloads 0.1.18 version and WSTRB signal go missing too.

Logs:
0.00ns INFO AXI lite master signals:
0.00ns INFO araddr width: 32 bits
0.00ns INFO arprot: not present
0.00ns INFO arready width: 1 bits
0.00ns INFO arvalid width: 1 bits
0.00ns INFO rdata width: 32 bits
0.00ns INFO rready width: 1 bits
0.00ns INFO rresp: not present
0.00ns INFO rvalid width: 1 bits

0.00ns INFO AXI lite master signals:
0.00ns INFO awaddr width: 32 bits
0.00ns INFO awprot: not present
0.00ns INFO awready width: 1 bits
0.00ns INFO awvalid width: 1 bits
0.00ns INFO wdata width: 32 bits
0.00ns INFO wready width: 1 bits
0.00ns INFO wstrb width: 4 bits
0.00ns INFO wvalid width: 1 bits
0.00ns INFO bready width: 1 bits
0.00ns INFO bresp: not present
0.00ns INFO bvalid width: 1 bits