alexforencich/cocotbext-axi

AxiStreamFrame assumes byte width 1 without TKEEP. Expected: self.width / 8 as default.

likewise opened this issue · 2 comments

likewise commented

If I connect a AXIS source to an AXIS sink, without (the optional) TKEEP, the self.byte_lanes is incorrectly 1 rather than all lanes enabled.
self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "sink"), dut.clk, dut.reset)

Root cause is AxiStreamFrame assumes byte width 1 if optional TKEEP[] is not present, but it should default to self.width // 8 because the AXIS specification mentions "when TKEEP is absent, TKEEP defaults to all bits HIGH" and "The width of the data payload is an integer number of bytes."

Fix: https://github.com/alexforencich/cocotbext-axi/blob/master/cocotbext/axi/axis.py#L290

- self.byte_lanes = 1
+ self.byte_lanes = self.width // 8

https://developer.arm.com/documentation/ihi0051/a/Default-Signaling-Requirements/Default-value-signaling/Optional-TKEEP-and-TSTRB?lang=en

I will also put a pull request on GitHub: #47

ollie-etl commented

@alexforencich this is addressed?

alexforencich commented

Yes it is, I forgot to close this one after merging the PR.