Axis DUT signal naming

[davidp135]

Hi,

The SystemVerilog / Verilog standard I use requires _i or _o at the end of port names. For example:

input  logic [DATA_WIDTH-1:0]  axis_tdata_i,
input  logic                   axis_tvalid_i,
output logic                   axis_tready_o,

I see you have the from_prefix to facilitate signal matching for the front end of the signal name. Is there a way to match the backend _i _o also?

Thanks

David

[davidp135]

Ah, maybe this is a duplicate of #20