[Question] How can I receive more than just four bytes? What I'm I doing wrong?
Opened this issue · 6 comments
sibeov commented
Intro
So! This is probably a user error on my part, but still.
Problem
This is is the source-code I'm working on. Simple transmit and receive. Yes! I know this is not how one uses pyuvm, but
I'm in the process of learning and now I'm focusing on learning this extensions. Maybe the problem is in how i use pyuvm?
@pyuvm.test()
class TestTransmitRandom(uvm_test):
"""Test the compilation of the TB and associated source files"""
def build_phase(self):
self.logger.info(f"Build phase of {self.get_name()}")
# self.bfm = BFM()
self.dut = cocotb.top
async def run_phase(self):
self.logger.info(f"Run phase of {self.get_name()}")
self.dut_in = AxiStreamSource(AxiStreamBus.from_prefix(self.dut, "axisi"),
self.dut.csi_sys_clk,
self.dut.rsi_sys_rst)
self.dut_out = AxiStreamSink(AxiStreamBus.from_prefix(self.dut, "axiso"),
self.dut.csi_sys_clk,
self.dut.rsi_sys_rst)
self.raise_objection()
self.logger.info("Starting clock")
cocotb.start_soon(Clock(self.dut.csi_sys_clk, 10, units="ns").start())
self.logger.info("Resetting DUT")
await FallingEdge(self.dut.csi_sys_clk)
self.dut.rsi_sys_rst = 0
await FallingEdge(self.dut.csi_sys_clk)
self.dut.rsi_sys_rst = 1
for cycle in range(4):
await RisingEdge(self.dut.csi_sys_clk)
await FallingEdge(self.dut.csi_sys_clk)
self.dut.rsi_sys_rst = 0
self.logger.info(f"Transmitting data:\n{self.data}")
test_data = b"Hello hello hello"
await self.dut_in.send(AxiStreamFrame(tdata=test_data))
self.logger.info(f"Expecting data:\n{self.data}")
rx_data = await self.dut_out.recv()
self.logger.info(f"Sendt data:\n{[b for b in test_data]}")
self.logger.info(f"Received data:\n{rx_data.tdata}")
self.drop_objection()When I execute i get this:
VPI module loaded!
0.00ns INFO cocotb Running on GHDL version 5.0.0-dev (4.1.0.r13.g0d97a760f.dirty) [Dunoon edition]
0.00ns INFO cocotb Running tests with cocotb v1.8.1 from /opt/oss-cad-suite/lib/python3.11/site-packages/cocotb
0.00ns INFO cocotb Seeding Python random module with 1716890959
0.00ns INFO cocotb.regression Found test tb_fifo_cc_dbuff.TestTransmitRandom
0.00ns INFO cocotb.regression running TestTransmitRandom (1/1)
Test the compilation of the TB and associated source files
0.00ns INFO ..on/pyuvm/tb_fifo_cc_dbuff.py(94) [uvm_test_top]: Build phase of uvm_test_top
0.00ns INFO ..n/pyuvm/tb_fifo_cc_dbuff.py(102) [uvm_test_top]: Run phase of uvm_test_top
vpi_get_str: unhandled property
vpi_get_str: unhandled property
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi AXI stream source
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi cocotbext-axi version 0.1.24
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi Copyright (c) 2020 Alex Forencich
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi https://github.com/alexforencich/cocotbext-axi
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi AXI stream source configuration:
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi Byte size: 8 bits
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi Data width: 32 bits (4 bytes)
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi AXI stream source signals:
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi tdata width: 32 bits
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi tdest: not present
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi tid: not present
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi tkeep: not present
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi tlast: not present
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi tready width: 1 bits
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi tuser: not present
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi tvalid width: 1 bits
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi Reset de-asserted
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso AXI stream sink
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso cocotbext-axi version 0.1.24
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso Copyright (c) 2020 Alex Forencich
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso https://github.com/alexforencich/cocotbext-axi
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso AXI stream sink configuration:
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso Byte size: 8 bits
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso Data width: 32 bits (4 bytes)
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso AXI stream sink signals:
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso tdata width: 32 bits
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso tdest: not present
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso tid: not present
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso tkeep: not present
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso tlast: not present
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso tready width: 1 bits
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso tuser: not present
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso tvalid width: 1 bits
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso Reset de-asserted
0.00ns INFO ..n/pyuvm/tb_fifo_cc_dbuff.py(113) [uvm_test_top]: Starting clock
0.00ns INFO ..n/pyuvm/tb_fifo_cc_dbuff.py(116) [uvm_test_top]: Resetting DUT
/home/sibeov/repos/vcp-verification/pyuvm/tb_fifo_cc_dbuff.py:118: DeprecationWarning: Setting values on handles using the ``dut.handle = value`` syntax is deprecated. Instead use the ``handle.value = value`` syntax
self.dut.rsi_sys_rst = 0
/home/sibeov/repos/vcp-verification/pyuvm/tb_fifo_cc_dbuff.py:121: DeprecationWarning: Setting values on handles using the ``dut.handle = value`` syntax is deprecated. Instead use the ``handle.value = value`` syntax
self.dut.rsi_sys_rst = 1
15.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi Reset asserted
15.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso Reset asserted
/home/sibeov/repos/vcp-verification/pyuvm/tb_fifo_cc_dbuff.py:127: DeprecationWarning: Setting values on handles using the ``dut.handle = value`` syntax is deprecated. Instead use the ``handle.value = value`` syntax
self.dut.rsi_sys_rst = 0
55.00ns INFO ..n/pyuvm/tb_fifo_cc_dbuff.py(129) [uvm_test_top]: Transmitting data:
AxiStreamFrame(tdata=bytearray(b']sW\xac\x8ay\x85\xf2\x9b\xadT\\D\xa7\xf8\xee2bH\x93L\xec^'), tkeep=None, tid=None, tdest=None, tuser=None, sim_time_start=None, sim_time_end=None)
55.00ns INFO ..n/pyuvm/tb_fifo_cc_dbuff.py(133) [uvm_test_top]: Expecting data:
AxiStreamFrame(tdata=bytearray(b']sW\xac\x8ay\x85\xf2\x9b\xadT\\D\xa7\xf8\xee2bH\x93L\xec^'), tkeep=None, tid=None, tdest=None, tuser=None, sim_time_start=None, sim_time_end=None)
55.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi Reset de-asserted
55.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso Reset de-asserted
60.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi TX frame: AxiStreamFrame(tdata=bytearray(b'Hello hello hello'), tkeep=None, tid=None, tdest=None, tuser=None, sim_time_start=60000000, sim_time_end=None)
80.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axiso RX frame: AxiStreamFrame(tdata=bytearray(b'Hell'), tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=80000000, sim_time_end=80000000)
80.00ns INFO ..n/pyuvm/tb_fifo_cc_dbuff.py(136) [uvm_test_top]: Sendt data:
[72, 101, 108, 108, 111, 32, 104, 101, 108, 108, 111, 32, 104, 101, 108, 108, 111]
80.00ns INFO ..n/pyuvm/tb_fifo_cc_dbuff.py(137) [uvm_test_top]: Received data:
bytearray(b'Hell')
80.00ns INFO cocotb.regression TestTransmitRandom passed
80.00ns INFO cocotb.regression *********************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
*********************************************************************************************
** tb_fifo_cc_dbuff.TestTransmitRandom PASS 80.00 0.01 8693.31 **
*********************************************************************************************
** TESTS=1 PASS=1 FAIL=0 SKIP=0 80.00 0.09 851.03 **
*********************************************************************************************It does not pass as only the first four octets have been received. I'm guessing I (the user) am the problem.
What I'm I doing wrong.
Deprecation Warning [SOLVED]
Also. Anyone can spot what I'm doing wrong to generate the deprecation warnings?
See answer: #87 (comment)
Specs
Let me know if you need to know anything in particular.
sibeov commented
Same happens with this snippet:
@cocotb.test()
async def TestTransmitRandom(dut):
"""Test the compilation of the TB and associated source files"""
cocotb.start_soon(Clock(dut.csi_sys_clk, 10, units="ns").start())
dut_in = AxiStreamSource(AxiStreamBus.from_prefix(dut, "axisi"),
dut.csi_sys_clk,
dut.rsi_sys_rst)
dut_out = AxiStreamSink(AxiStreamBus.from_prefix(dut, "axiso"),
dut.csi_sys_clk,
dut.rsi_sys_rst)
await FallingEdge(dut.csi_sys_clk)
dut.rsi_sys_rst = 0
await FallingEdge(dut.csi_sys_clk)
dut.rsi_sys_rst = 1
for cycle in range(4):
await RisingEdge(dut.csi_sys_clk)
await FallingEdge(dut.csi_sys_clk)
dut.rsi_sys_rst = 0
test_data = b"Hello hello hello"
await dut_in.send(AxiStreamFrame(tdata=test_data))
rx_data = await dut_out.recv()
print(f"Test data : {test_data}")
print(f"Received data : {rx_data.tdata}")Gatherer commented
to get rid of the deprecation warning change to dut.rsi_sys_rst.value = 1
sibeov commented
Of course. Thanks!
Gatherer commented
Hello,
from the log I see you do not have the tlast signal on both interfaces.
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi tlast: not present
Maybe that is the reason you only get one beat, 32 bit / 4 byte back. As the tlast is not present the receive function may written in a way to return after one beat in this case.
sibeov commented
Ahaa. I will check that as soon as I can.
sibeov commented
Ahaa. I will check that as soon as I can.
Have not had time to check this out. Still working on it.