alvislin

Pinned Repositories

• 2-way-Set-Associative-Cache-Controller

  Synthesizable and Parameterized Cache Controller in Verilog

  Language:Verilog00

• 4-way-set-associative-cache-verilog

  Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy

  Language:Verilog00

• A-variant-of-NIST-SP-800-22-test-suit

  A variant of NIST SP 800-22 revison.1a test suit

  Language:C00

• Advanced-Encryption-Standard

  Hardware Implementation of AES based on (FIPS) 197

  Language:SystemVerilog00

• aes

  Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

  Language:Verilog00

• aes-armcortexm

  Fast, constant-time and masked AES assembly implementations for ARM Cortex-M3 and M4

  Language:Assembly00

• Ai-Thinker-Open-TG7100C_SDK

  安信可模组量产发布SDK

  Language:C00

• Airkiss

  A source code implementation of Wechat(微信) Airkiss protocol

  Language:C00

• CortexM3_SoC

  Language:Verilog38

• RTL8720-SDK

  深圳市安信可科技有限公司，RTL8720系列模组开发包

  Language:C10

alvislin's Repositories