anhducdinh

100-Days-of-RTL

100DaysofRTL

100DaysofRTL: basic logic gates, mux, half and full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector with Moore, Edge Detector with Mealy

AMBA-BUS-PROTOCOL

In this project different bus architectures : APB , AHP , AXI that are part of AMBA (Advanced Microcontroller Bus Architecture) are implemented

AMBA_APB_Protocol

APB-Master-Bridge

The master of APB bus is the bridge between the previous system bus and APB bus. This bridge is also a slave to the previous system bus. So, it has two interfaces, previous bus slave interface and APB master interface. Its functionality is to convert complex transfer of the previous system bus to simpler one of APB bus.

ASIC

EE 287 2012 Fall

axi_systemverilog

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

core_sdram_axi4

SDRAM controller with AXI4 interface

Design-and-Simulation-of-a-32-bit-RISC-V-Core-and-APB

A 32 Bit RISCV Core with APB protocol for data transfer written with SystemVerilog and verilog.

MIPS32

Design of 32-bit MIPS Processor

anhducdinh/AMBA-BUS-PROTOCOL

In this project different bus architectures : APB , AHP , AXI that are part of AMBA (Advanced Microcontroller Bus Architecture) are implemented

anhducdinh/axi_systemverilog

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

anhducdinh/100-Days-of-RTL

anhducdinh/15DaysofUVM

anhducdinh/APB-Protocol-Verification-using-UVM

APB verification using UVM

anhducdinh/ASIC-Design-Roadmap

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

anhducdinh/Complete-ASIC-Flow-of-I2C-communication-protocol

This is the graduation project for ASIC Subject for CND training which is about apply ASIC flow for I2C commnuication protocol

anhducdinh/core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

anhducdinh/CRC_CCIT_16_enc_dec

anhducdinh/cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

anhducdinh/Design-and-ASIC-Implementation-of-UART

This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II

anhducdinh/doan_1

none

anhducdinh/I2C_Bus

I2C_Bus Design and Verification

anhducdinh/IP_timer

A 32-bit Timer/Counter/Capture Soft IP (Verilog)

anhducdinh/my-verilog-examples

A place to keep my synthesizable verilog examples.

anhducdinh/PiDRAM

PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory techniques. Prototype on a RISC-V rocket chip system implemented on an FPGA. Described in our paper: https://arxiv.org/abs/2111.00082

anhducdinh/project_1_scolling_door_using_Arduino_ATMega328p

Do an 1: Do an dien tu

anhducdinh/RISC-V

Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.

anhducdinh/rv_soc

Roa Logic RISC-V SoC

anhducdinh/Sequential-Logic-Circuits

Verilog design and testbench files for Flip Flop, Counters, RAM, FIFO, Shift Registers and other sequential logic circuits

anhducdinh/SPI_Serial_Peripheral_Interface_Verilog_Modules

Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device

anhducdinh/Testgit

anhducdinh/uart_rx_tx

anhducdinh/UVM

Standard Universal Verification Methodology

anhducdinh/UVM-Verification-of-AXI4-Lite-Interface-

UVM Verification of AXI4-Lite Interface

anhducdinh/uvm_verification_ahb_apb_bridge

UVM Verification enviroinment for AHB to APB bridge. Supports upto 8 APB slave Devices.

anhducdinh/Verification-of-UART-core-using-UVM

Verification of UART core using UVM

anhducdinh/Verification_of_I2C_Protocol_IP

anhducdinh/verilog-axi

Verilog AXI components for FPGA implementation

anhducdinh/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO