avashist003

Bit_Manipulation_cpp

C++ implementation for useful bit manipulation logic

deep-learning-v2-pytorch

Projects and exercises for the latest Deep Learning ND program https://www.udacity.com/course/deep-learning-nanodegree--nd101

FIFO_SystemVerilog_Assertion

Synchronous FIFO design & verification using systemVerilog Assertions

Generic_syncFIFO

Generic synchronous FIFO where the depth may or may not be power of 2

Memory_Arbiter_Verilog

Request/Grant based Memory Bus Arbiter designed as FSM using Verilog.

Onboard-SDK-ROS

Official ROS packages for DJI onboard SDK.

Perl_Verification

SystemVerilog_Design_Verification

Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog

UVM_Verification

Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence

avashist003/UVM_Verification

Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence

avashist003/SystemVerilog_Design_Verification

Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog

avashist003/FIFO_SystemVerilog_Assertion

Synchronous FIFO design & verification using systemVerilog Assertions

avashist003/Perl_Verification

avashist003/Generic_syncFIFO

Generic synchronous FIFO where the depth may or may not be power of 2

avashist003/Memory_Arbiter_Verilog

Request/Grant based Memory Bus Arbiter designed as FSM using Verilog.

avashist003/Bit_Manipulation_cpp

C++ implementation for useful bit manipulation logic

avashist003/deep-learning-v2-pytorch

Projects and exercises for the latest Deep Learning ND program https://www.udacity.com/course/deep-learning-nanodegree--nd101

avashist003/Onboard-SDK-ROS

Official ROS packages for DJI onboard SDK.