AXI Model control parameters

[useragdp1]

I have the simulations with AXI models working. However, I see that model returns the read response and wr ack with fixed 1-2 clock latency. And all read responses are in-order.
Is there some control knobs in AXI model which can return these responses with random latency and out-of-order.
Also, I need control for various ready signals to be toggled randomly.
Thanks

[czfpga]

Hi abhaypelago,

Thank you for reaching out. Could you clarify the question a bit? Which simulation are you running? Which AXI bus you would like to have the arbitrary response latency and out-of-order transaction? So I can dig further find out.

Thanks,

• Chen

[useragdp1]

I am running with my own CL using the dram_dma Testbench provided by AWS. I use the AXI_MEMORY_MODEL option. I see that on both PCIM and DDR responses, the ready is always high and AXI responses are returned in the next clock.

[czfpga]

Thank you for that information. I'll need to dig a bit into it to see if there is any built-in control knob in the testbench setup that can be directly utilized. I'll let you know asap.

• Chen

[AWScsaralay]

Hello,

All the Verification Modules, including the Shell BFM are provided here

The testbench does not provide parameters to vary the response time or behavior of AXI4. However, you could try modifying the behavior of the interfaces in sh_bfm.sv.

For example:

• sh_bfm.sv#Line1099 shows condition when sh_cl_pcim_awready is set.
• sh_bfm.sv#Line1224 shows when sh_cl_pcim_rvalid is assert by the testbench.
  You could tweak the behavior as per your requirement.

However, please note that BFM changes you make does not conflict with the Shell Interface Spec. Otherwise your design behavior could differ between simulations and real F1 instance.

Please let us know if you have any questions or need anything.

Thanks!
Chakra

[AWScsaralay]

Hello, we'll mark this post as resolved. Please reach out to us if you have any questions. Thank you.